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MCF5274LVM166 bảng dữ liệu(PDF) 8 Page - Motorola, Inc |
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MCF5274LVM166 bảng dữ liệu(HTML) 8 Page - Motorola, Inc |
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8 / 76 page  MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 1.1 Preliminary Features Freescale Semiconductor 8 — Supports 16-bit wide memory devices — Supports Dual Data Rate (DDR) SDRAM. — Page mode support — Programmable refresh interval timer. — Sleep mode and self-refresh. — Supports 16-byte (4-beat, 4-byte) critical-word-first burst transfer. — Memory sizes from 8 Mbyte to 128 MByte (per chip select) — 166 MHz data transfer rate (DDR) — Two independent chip selects •Reset — Separate Reset In and Reset Out signals — Six sources of reset (POR, External, Software, Watchdog, Loss of clock/lock) — Status flag indication of source of last reset • Chip Configurations — System configuration during reset — Bus Monitor, Abort Monitor — Configurable output pad drive strength — Unique Part Identification and Part Revision Numbers • General Purpose I/O interface — Up to 69 bits of general purpose I/O — Coherent 32-bit control — Bit manipulation supported via set/clear functions — Unused peripheral pins may be used as extra GPIO • JTAG support for system level board testing — Unique JTAG Part Identification and Part Revision Numbers 3.2 V2 Core Overview The ColdFire V2 core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage Instruction Fetch Pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the Operand Execution Pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage (AGEX) performs instruction execution and calculates operand effective addresses, if needed. The V2 core implements the ColdFire Instruction Set Architecture Revision A with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the V2 core includes the enhanced multiply-accumulate unit (EMAC) for improved signal processing capabilities. The EMAC implements a 4-stage execution pipeline, optimized for 32 x 32 bit operations, |
Số phần tương tự - MCF5274LVM166 |
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Mô tả tương tự - MCF5274LVM166 |
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