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AD2S44-TM11B bảng dữ liệu(PDF) 8 Page - Analog Devices |
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AD2S44-TM11B bảng dữ liệu(HTML) 8 Page - Analog Devices |
8 / 13 page Data Sheet AD2S44 Rev. B | Page 7 of 12 THEORY OF OPERATION The AD2S44 operates on a tracking principle. The output digital word continually tracks the position of the synchro/resolver shaft without the need for external convert commands and status wait loops. As the transducer moves through a position equivalent to the least significant bit weighting, the output digital word is updated. Each channel is identical in operation, sharing power supply and output pins. Both channels operate continuously and independently of each other. The digital output from either channel is available after switching the channel select and output enable inputs. If the device is a synchro-to-digital converter, the 3-wire synchro output is connected to the S1, S2, and S3 pins on the unit, and a solid-state Scott T input conditioner converts these signals into resolver format given by V1 = K E0 sin ωt sin θ V2 = K E0 sin ωt cos θ where: θ is the angle of the synchro shaft. E0 sin ωt is the reference signal. K is the transformation ratio of the input signal conditioner. If the unit is a resolver-to-digital converter, the 4-wire resolver output is connected directly to the S1, S2, S3, and S4 pins on the unit. To understand the conversion process, assume that the current word state of the up-down counter is ϕ. V1 is multiplied by cos ϕ, and V2 is multiplied by sin ϕ to give the following: K E0 sin ωt sin θ cos ϕ K E0 sin ωt cos θ sin ϕ These signals are subtracted by the error amplifier to give K E0 sin ωt (sin θ cos ϕ − cos θ sin ϕ) or K E0 sin ωt sin (θ − ϕ) A phase sensitive detector, integrator, and voltage-controlled oscillator (VCO) form a closed-loop system that seeks to null sin (θ − ϕ). When this is accomplished, the word state of the up-down counter (ϕ) equals the synchro/resolver shaft angle (θ), to within the rated accuracy of the converter. CONNECTING THE CONVERTER The power supply voltages connected to −VS and +VS are to be ±15 V and cannot be reversed. It is suggested that a parallel combination of a ceramic 100 nF capacitor and a tantalum 6.8 µF capacitor be placed from each of the supply pins to GND. The pin marked GND is connected electrically to the case and is to be taken to 0 V potential in the system. The digital output is taken from Pin 26 to Pin 32 and from Pin 1 to Pin 7. Pin 26 is the MSB, and Pin 7 is the LSB. The reference connections are made to the RHI pins and the RLO pins. In the case of a synchro, the signals are connected to the S1, S2, and S3 pins, according to the following convention: ES1−S3 = ERLO−RHIsin ωt sin θ ES3−S2 = ERLO−RHIsin ωt sin (θ − 120°) ES2−S1 = ERLO−RHIsin ωt sin (θ – 240°) For a resolver, the signals are connected to the S1, S2, S3, and S4 pins, according to the following convention: ES1−S3 = ERLO−RHIsin ωt sin θ ES2−S4 = ERLO−RHIsin ωt cos θ CHANNEL SELECT (A/B) A/B is the channel select input. A Logic 1 selects Channel A, and a Logic 0 selects Channel B. Data becomes valid 640 ns after A/B is toggled. Timing information is shown in Figure 4 and Figure 5. AD2S44 REFERENCE CONDITIONER SYNCHRO/ RESOLVER CONDITIONER PHASE- SENSITIVE DETECTOR THREE- STATE OUTPUT LATCHES DB1 (MSB) TO DB14 (LSB) PHASE- SENSITIVE DETECTOR HIGH SPEED SIN/COS MULTIPLIER V1 V2 BUILT-IN TEST DETECTION ERROR AMP UP-DOWN COUNTER UP-DOWN COUNTER INTEGRATOR VCO VCO INTEGRATOR ERROR AMP HIGH SPEED SIN/COS MULTIPLIER SYNCHRO/ RESOLVER CONDITIONER REFERENCE CONDITIONER S3 (A) RHI (A) RLO (A) RHI (B) RLO (B) +VS –VS GND S4 (A) S1 (A) S2 (A) S3 (B) S4 (B) S1 (B) S2 (B) OE A/B BIT Figure 3. Functional Block Diagram |
Số phần tương tự - AD2S44-TM11B |
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Mô tả tương tự - AD2S44-TM11B |
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