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AD6677EBZ bảng dữ liệu(PDF) 8 Page - Analog Devices |
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AD6677EBZ bảng dữ liệu(HTML) 8 Page - Analog Devices |
8 / 48 page AD6677 Data Sheet Rev. C | Page 8 of 48 Parameter Temperature Min Typ Max Unit Low Level Output Voltage (VOL) Full IOL = 2.0 mA Full 0.25 V IOL = 1.6 mA Full 0.2 V IOL = 50 µA Full 0.05 V 1 Pull-up. 2 Needs an external pull-up. 3 Pull-down. 4 Compatible with JEDEC standard JESD8-7A. SWITCHING SPECIFICATIONS Table 4. Parameter Symbol Temperature Min Typ Max Unit CLOCK INPUT PARAMETERS Conversion Rate1 fS Full 40 250 MSPS SYSREF± Setup Time to Rising Edge CLK±2 tREFS Full 300 ps SYSREF± Hold Time from Rising Edge CLK±2 tREFH Full 40 ps SYSREF± Setup Time to Rising Edge RFCLK±2 tREFSRF Full 400 ps SYSREF± Hold Time from Rising Edge RFCLK±2 tREFHRF Full 0 ps CLK± Pulse Width High tCH Divide by 1 Mode, DCS Enabled Full 1.8 2.0 2.2 ns Divide by 1 Mode, DCS Disabled Full 1.9 2.0 2.1 ns Divide by 2 Mode Through Divide by 8 Mode Full 0.8 ns Aperture Delay tA Full 1.0 ns Aperture Uncertainty (Jitter) tJ Full 0.16 ps rms DATA OUTPUT PARAMETERS Data Output Period or Unit Interval (UI) Full 20 × fS Seconds Data Output Duty Cycle 25°C 50 % Data Valid Time 25°C 0.78 UI PLL Lock Time tLOCK 25°C 25 µs Wake-Up Time (Standby) 25°C 10 µs Time ADC (Power-Down)3 25°C 250 ms Time Output (Power-Down)4 25°C 50 ms Subclass 0: SYNCINB± Falling Edge to First Valid K.28 Characters (Delay Required for Rx CGS Start) Full 5 Multiframes Subclass 1: SYSREF± Rising Edge to First Valid K.28 Characters (Delay Required for SYNCB± Rising Edge/Rx CGS Start) Full 6 Multiframes CGS Phase K.28 Characters Duration Full 1 Multiframe Pipeline Delay JESD204B (Latency) Full 36 Cycles5 Additional Pipeline Latency with NSR Enabled Full 2 Cycles Fast Detect (Latency) Full 7 Cycles Lane Rate Full 5 Gbps Uncorrelated Bounded High Probability (UBHP) Jitter Full 12 ps Random Jitter at 5 Gbps Full 1.7 ps rms Output Rise/Fall Time Full 60 ps Differential Termination Resistance 25°C 100 Ω Out of Range Recovery Time Full 3 Cycles 1 Conversion rate is the clock rate after the divider. 2 Refer to Figure 3 for timing diagram. 3 Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode. 4 Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode. 5 Cycles refers to ADC conversion rate cycles. |
Số phần tương tự - AD6677EBZ |
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Mô tả tương tự - AD6677EBZ |
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