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AD6676EBZ bảng dữ liệu(PDF) 6 Page - Analog Devices

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AD6676
Data Sheet
Rev. D | Page 6 of 90
Parameter
Temperature
Test Conditions/Comments
Min
Typ
Max
Unit
CLOCK SYNTHESIZER
Phase Detector Frequency
Full
10
80
MHz
Minimum Charge Pump Output Current
Full
0.1
mA
Maximum Charge Pump Output Current
Full
6.4
mA
VCO Tuning Range
Full
2.94
3.2
GHz
Σ-∆ ADC AND DIGITAL DOWNCONVERTER
Resolution
Full
16
Bits
Clock Frequency (FADC)
Full
2.0
3.2
GHz
IF Center Frequency (FIF)
Full
70
450
MHz
IF Bandwidth
Maximum BW applies to
higher FIF
0.005
× FADC
0.05 ×
FADC
IF Pass Band Gain Flatness
Full
FADC, FIF, and BW dependent
1.0
dB
Out-of-Band Peaking
Depends on FADC, FIF, and BW
0.5
dB
Alias Rejection
Regions of FADC ± FIF
51
dB
Fixed Decimation Factors
Full
12, 16, 24,
32
NCO Tuning Resolution
Decimate by 12 or 24
FADC/3072
Decimate by 16 or 32
FADC/4096
Out-of-Range Recovery Time
Full
Relative to ADC clock cycles
52
1/FADC
POWER SUPPLY AND CONSUMPTION
Analog Supply Voltage
VDD1, VDDL, VDDQ, VDDC
Full
1.0725
1.1
1.1275
V
VDD2, VDD2NV
Full
2.4375
2.5
2.5625
V
VSS2IN
Use on-chip regulator, tie to
VSS2OUT
−2.0
V
Digital Supply Voltage (VDDD)
Full
1.0725
1.1
1.1275
V
JESD204B Supply Voltage (VDDHSI)
Full
1.0725
1.1
1.1275
V
SPI Interface Supply Voltage (VDDIO)
Full
1.7
1.8
2.5625
V
Analog Supply Current
IVDD1 + IVDDL
Full
368
397
mA
IVDDC + IVDDQ
Full
CLK synthesizer disabled
57
68
mA
IVDDC4 + IVDDQ
Full
CLK synthesizer enabled
93
106
mA
IVDD2 + IVDD2NV
Full
145
165
mA
Digital Supply Current (IVDDD)
Full
141
208
mA
JESD204B Supply Current (IVDDHSI)
Full
164
190
mA
SPI Interface Supply Current (IVDDIO)
Full
0.4
1
mA
Power Consumption
Full
With CLK SYN Disabled
1.16
1.31
W
With CLK SYN Enabled
1.20
1.34
W
Standby5
Full
0.44
W
Power-Down
Full
66
177
mW
OPERATING TEMPERATURE RANGE
−40
+85
°C
1 Extrapolated input power level is measured at the center of IF pass band that results in a 0 dBFS power level.
2 The overload level of the Σ-Δ
ADC for a CW tone is guaranteed up to −2 dBFS back off from full scale but typically exceeds −1 dBFS. Input signals that have a higher
peak-to-average ratio (PAR) than a CW tone (PAR = 3 dB) must apply additional back off based on the difference in PAR.
3 The clock synthesizer reference divider (Register 0x2BB, Bits[7:6]) must be set to divide by 4 or by 2 to ensure that its phase detector frequency remains ≤40 MHz.
4 fCLK = 200 MHz, FADC = 3.2 GHz.
5 The AD6676 is configured for recovery time of 11.5 μs with VSS2 generator/ digital data in standby (Register 0x150 = 0x40) and low power ADC state (Register 0x250 = 0x95).


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