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ADE9000ACPZ-RL bảng dữ liệu(PDF) 7 Page - Analog Devices |
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ADE9000ACPZ-RL bảng dữ liệu(HTML) 7 Page - Analog Devices |
7 / 73 page ADE9000 Data Sheet Rev. A | Page 6 of 72 Parameter Min Typ Max Unit Test Conditions/Comments ADC PGA Gain Settings (PGA_GAIN) 1, 2, or 4 V/V PGA gain setting is referred to as PGA_GAIN Differential Input Voltage Range (VxP to VxN, IxP to IxN) −1/Gain +1/Gain V 707 mV rms, when VREF = 1.25 V, this voltage corresponds to 53 million codes Maximum Operating Voltage on Analog Input Pins (VxP, VxN, IxP, and IxN) −0.6 +0.6 V Voltage on the pin with respect to ground (GND = AGND = DGND = REFGND) Signal-to-Noise Ratio (SNR)2 PGA = 1 96 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 101 dB 8 kSPS, sinc4 + infinite impulse response (IIR), low-pass filter (LPF) output, VIN = −0.5 dB from FS PGA = 4 93 dB 32 kSPS, sinc4 output 96 dB 8 kSPS, sinc4 + IIR LPF output Total Harmonic Distortion (THD)2 PGA = 1 −101 −95 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS −101 −95 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS PGA = 4 −107 −99 dB 32 kSPS, sinc4 output −107 −99 dB 8 kSPS, sinc4 + IIR LPF output Signal-to-Noise and Distortion Ratio (SINAD)2 PGA = 1 95 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 98 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS PGA = 4 93 dB 32 kSPS, sinc4 output 96 dB 8 kSPS, sinc4 + IIR LPF output Spurious-Free Dynamic Range (SFDR)2 PGA = 1 100 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from FS 100 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from FS Output Pass Band (0.1dB) Sinc4 Outputs 1.344 kHz 32 kSPS, sinc4 output Sinc4 + IIR LPF Outputs 1.344 kHz 8 kSPS output Output Bandwidth (−3 dB) 2 Sinc4 Outputs 7.2 kHz 32 kSPS, sinc4 output Sinc4 + IIR LPF Outputs 3.2 kHz 8 kSPS output Crosstalk2 −120 dB At 50 Hz or 60 Hz, see the Terminology section AC Power Supply Rejection Ratio (AC PSRR)2 −120 dB At 50 Hz, see the Terminology section Common-Mode Rejection Ratio (AC CMRR)2 115 dB At 100 Hz and 120 Hz Gain Error ±0.3 ±1 %typ See the Terminology section Gain Drift2 ±3 ppm/°C See the Terminology section Offset ±0.040 ±3.8 mV See the Terminology section Offset Drift2 0 ±2 µV/°C See the Terminology section Channel Drift (PGA, ADC, Internal Voltage Reference) ±7 ±25 ppm/°C PGA = 1, internal VREF ±7 ±25 ppm/°C PGA = 2, internal VREF ±7 ±25 ppm/°C PGA = 4, internal VREF Differential Input Impedance (DC) 165 185 kΩ PGA = 1, see the Terminology section 80 90 kΩ PGA = 2 40 45 kΩ PGA = 4 |
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