MYSON

TECHNOLOGY

MTV24C08/

24LC08

(Preliminary)

MTV24C08/24LC08 Revision.1.0 11/03/1999

5/15

WRITE OPERATIONS

Byte Write

Following the start signal from the master, the slave address is placed onto the bus by the

master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the ninth clock cycle.

Therefore the next byte transmitted by the master is the word address and will be written into the address

pointer of the MTV24C08/24LC08. After receiving another acknowledge signal from the MTV24C08/24LC08

the master device will transmit the data word to be written into the addressed memory location. The

MTV24C08/24LC08 acknowledges again and the master generates a stop condition. This initiates the

internal write cycle, and during this period the MTV24C08/24LC08 will not generate acknowledge signals.

(Shown in Figure 4)

Page Write

The write control byte, word address and the first data byte are transmitted to the MTV24C08/24LC08 in the

same way as in a byte write. But instead of generating a stop condition the master transmit up to 16 data

bytes to the MTV24C08/24LC08 which are temporarily stored in the on-chip page buffer and will be written

into the memory after the master has transmitted a stop condition. After the receipt of each byte, the two

lower order address pointer bits are internally incremented by one. The higher order six bits of the word

address remains constant. If the master should transmit more than 16 bytes prior to generating the stop

condition, the address counter will roll over and the previously received data will be overwritten. As with the

byte write operation, once the stop condition is received an internal write cycle will begin. (Shown in Figure

5).

Acknowledge Polling

Since the device will not acknowledge during a write cycle , this can be used to determine when the cycle is

complete (this feature can be used to maximize bus throughout). Once the stop condition for a write

command has been issued from the master, the device initiates the internally timed write cycle. ACK polling

can be initiated immediately. This involves the master sending a start condition followed by the control byte

for a write command (R/W = 0). If the device is still busy with the write cycle , then no ACK will returned. If

the cycle is complete then the device will return the ACK and the master can then proceed with the next

read or write commands.

Write Protection

Programming will not take place if the WP pin of the MTV24C08/24LC08 is connected to Vcc. The

MTV24C08/24LC08 will accept slave and byte addresses; but if the memory accessed is write protected by

the WP pin, the MTV24C08/24LC08 will not generate an acknowledge after the first byte of data has been

received, and thus the programming cycle will not be started when the stop condition is asserted.

READ OPERATIONS

Read operations are initiated in the same way as write operations with the exception that the R/W bit of the

slave address is set to one. There are three basic types of read operations: current address read, random

read, and sequential read.