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AD4007BRMZ bảng dữ liệu(PDF) 6 Page - Analog Devices |
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6 / 38 page AD4003/AD4007/AD4011 Data Sheet Rev. B | Page 6 of 38 Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL OUTPUTS Data Format Serial 18 bits, twos complement Pipeline Delay Conversion results available immediately after completed conversion Output Low Voltage, VOL ISINK = 500 μA 0.4 V Output High Voltage, VOH ISOURCE = −500 μA VIO − 0.3 V POWER SUPPLIES VDD 1.71 1.8 1.89 V VIO 1.71 5.5 V Standby Current VDD = 1.8 V, VIO = 1.8 V, T = 25°C 1.6 μA Power Dissipation VDD = 1.8 V, VIO = 1.8 V, VREF = 5 V 10 kSPS, high-Z mode disabled 80 μW 500 kSPS, high-Z mode disabled 4 4.7 mW 1 MSPS, high-Z mode disabled 8 9.3 mW 2 MSPS, high-Z mode disabled 16 18.5 mW 500 kSPS, high-Z mode enabled 5 6.2 mW 1 MSPS, high-Z mode enabled 10 12.3 mW 2 MSPS, high-Z mode enabled 20 24.5 mW VDD Only 500 kSPS, high-Z mode disabled 2.4 mW 1 MSPS, high-Z mode disabled 4.9 mW 2 MSPS, high-Z mode disabled 9.5 mW REF Only 500 kSPS, high-Z mode disabled 1.4 mW 1 MSPS, high-Z mode disabled 2.8 mW 2 MSPS, high-Z mode disabled 5.5 mW VIO Only 500 kSPS, high-Z mode disabled 0.1 mW 1 MSPS, high-Z mode disabled 0.4 mW 2 MSPS, high-Z mode disabled 1.0 mW Energy per Conversion 8 nJ/sample TEMPERATURE RANGE Specified Performance TMIN to TMAX −40 +125 °C 1 The acquisition phase is the time available for the input sampling capacitors to acquire a new input with the ADC running at a throughput rate of 2 MSPS for the AD4003, 1 MSPS for the AD4007, and 500 kSPS for the AD4011. 2 A throughput rate of 2 MSPS can only be achieved with turbo mode enabled and a minimum SCK rate of 75 MHz. Refer to Table 4 for the maximum achievable throughput for different modes of operation. 3 Transient response is the time required for the ADC to acquire a full-scale input step to ±1 LSB accuracy. 4 The minimum and maximum values are guaranteed by characterization, but not production tested. 5 See the 1/f noise plot in Figure 23. |
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