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AD9953ASV bảng dữ liệu(PDF) 9 Page - Analog Devices |
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AD9953ASV bảng dữ liệu(HTML) 9 Page - Analog Devices |
9 / 42 page PRELIMINARY TECHNICAL DATA AD9953 36 RESET I Active high hardware reset pin. Assertion of the RESET pin forces the AD9953 to the initial state, as described in the IO Port Register map. 37 IOSYNC I Asynchronous active high reset of the serial port controller. When high, the current IO operation is immediately terminated enabling a new IO operation to commence once IOSYNC is returned low 38 SDO O When operating the I/O port as a 3-wire serial port this pin serves as the serial data output. When operated as a 2-wire serial port this pin is the unused and can be left unconnected. 39 CS-BAR I This pin functions as an active low chip select that allows multiple devices to share the IO bus. 40 SCLK I This pin functions as the serial data clock for IO operations 41 SDIO I/O When operating the I/O port as a 3-wire serial port this pin serves as the serial data input, only. When operated as a 2-wire serial port this pin is the bi- directional serial data pin. 43 DVDD_I/O I Digital power supply (for IO cells only, 3.3v optional) 44 SYNC_IN I Input signal used to synchronize multiple AD9953s. This input is connected to the SYNC_CLK output of a different AD9953. 45 SYNC_CLK O Clock output pin, which serves as a synchronizer for external hardware. 46 OSK I Input pin used to control the direction of the Shaped On-Off Keying function when programmed for operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin should be tied to DGND. 47,48 PS0, PS1 I Input pins used to select one of the four internal profiles. Profile<1:0>are synchronous to the SYNC_CLK pin. Any change in these inputs transfers the contents of the internal buffer memory to the IO Registers (sends an internal I/O UPDATE). Table 1 Hardware Pin Descriptions REV. PrB 1/30/03 Page 9 Analog Devices, Inc. |
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