303 South Technology Court Broomfield, CO 80021

Phone: (800) SMI-MMIC

http://www.sirenza.com

2

EDS-103643 Rev B

Preliminary

STA-6033 4.9-5.9 GHz Power Amp

Pin Out Description

Pin #

Function

Description

1,4,9,12,13

N/C

Pins are not used. May be grounded, left open, or connected to adjacent pin.

5VPC1

VPC1 is the bias control pin for the stage 1 active bias circuit. An external series resistor is required for proper

setting of bias levels. Refer to the evaluation board schematic for resistor value.

To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage applied to pin 16

(Vbias) unless Vpc supply current capability is less than 10 mA.

6VPC2

VPC2 is the bias control pin for the stage 2 active bias circuit. An external series resistor is required for proper

setting of bias levels. Refer to the evaluation board schematic for resistor value.

To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage applied to pin 16

(Vbias) unless Vpc supply current capability is less than 10 mA.

7VPC3

VPC3 is the control pin for the stage 3 active bias circuits. An external series resistor is required for proper set-

ting of bias levels. Refer to the evaluation board schematic for resistor value.

To prevent potential damage, do not apply voltage to this pin that is +1V greater than voltage applied to pin 16

(Vbias) unless Vpc supply current capability is less than 10 mA.

8

Vdet

Ouput power detector voltage. Load with 10K-100K ohms to ground for best performance.

2,3

RFIN

RF input pins. This is DC grounded internal to the IC. Do not apply voltage to this pin. All three pins must be

used for proper operation.

10,11

RFOUT

RF output pin. This is also another connection to the 3rd stage collector

14

VC3

3rd stage collector bias pin. Apply 3.0V to 3.6V to this pin.

15

VC2

2nd stage collector bias pin. Apply 3.0V to 3.6V to this pin.

16

VC1,Vbias

1st stage collector bias pin and active bias network VCC. Apply 3.0V to 3.6V to this pin.

EPAD

Gnd

Exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for

optimum thermal and RF performance. Several vias should be located under the EPAD as shown in the rec-

ommended land pattern (page 5).

Caution: ESD Sensitive

Appropriate precaution in handling, packaging

and testing devices must be observed.

Absolute Maximum Ratings

Parameters

Value

Unit

VC3 Collector Bias Current (pin16)

400

mA

VC2 Collector Bias Current (pin18)

140

mA

VC1 Collector Bias Current (pin19)

50

mA

V

Power Dissipation

1.4

W

-40 to +85

ºC

RF Input Power for 50 ohm load

20

dBm

Storage Temperature Range

-40 to +150

ºC

ºC

ESD Human Body Model

>1000

V

Operation of this device beyond any one of these limits may

cause permanent damage. For reliable continuous operation

the device voltage and current must not exceed the maximum

operating values specified in the table on page one.

Bias conditions should also satisfy the following expression:

Simplified Device Schematic

Stage 1

Bias

Stage 2

Bias

Stage 3

Bias

Pin 2, 3

Pin 10,11

Pin

5

Pin

16

Pin

6

Pin

15

Pin

7

Pin

14

Pin

8

EPAD

EPAD

EPAD