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X1240 bảng dữ liệu(PDF) 5 Page - Xicor Inc. |
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X1240 bảng dữ liệu(HTML) 5 Page - Xicor Inc. |
5 / 19 page X1240 5 RWEL: Register Write Enable Latch—Volatile This bit is a volatile latch that powers up in the LOW (disabled) state. The RWEL bit must be set to “1” prior to any writes to the Clock/Control Registers. Writes to RWEL bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. A write to the CCR requires both the RWEL and WEL bits to be set in a specific sequence. WEL: Write Enable Latch—Volatile The WEL bit controls the access to the CCR and mem- ory array during a write operation. This bit is a volatile latch that powers up in the LOW (disabled) state. While the WEL bit is LOW, writes to the CCR or any array address will be ignored (no acknowledge will be issued after the Data Byte). The WEL bit is set by writing a “1” to the WEL bit and zeroes to the other bits of the Status Register. Once set, WEL remains set until either reset to 0 (by writing a “0” to the WEL bit and zeroes to the other bits of the Status Register) or until the part pow- ers up again. Writes to WEL bit do not cause a non-vol- atile write cycle, so the device is ready for the next operation immediately after the stop condition. RTCF: Real Time Clock Fail Bit—Volatile This bit is set to a ‘1’ after a total power failure. This is a read only bit that is set by hardware when the device powers up after having lost all power to the device. The bit is set regardless of whether VCC or VBACK is applied first. The loss of one or the other supplies does not result in setting the RTCF bit. The first valid write to the RTC (writing one byte is sufficient) resets the RTCF bit to ‘0’. Unused Bits: These devices do not use bits 3 through 6, but must have a zero in these bit positions. The Data Byte output during a SR read will contain zeros in these bit locations. CONTROL REGISTERS Block Protect Bits - BP2, BP1, BP0 - (Nonvolatile) The Block Protect Bits, BP2, BP1 and BP0, determine which blocks of the array are write protected. A write to a protected block of memory is ignored. The block pro- tect bits will prevent write operations to one of eight segments of the array. The partitions are described in Table 3. Table 3. Block Protect Bits WRITING TO THE CLOCK/CONTROL REGISTERS Changing any of the nonvolatile bits of the clock/control register requires the following steps: —Write a 02H to the Status Register to set the Write Enable Latch (WEL). This is a volatile operation, so there is no delay after the write. (Operation pre- ceeded by a start and ended with a stop). —Write a 06H to the Status Register to set both the Register Write Enable Latch (RWEL) and the WEL bit. This is also a volatile cycle. The zeros in the data byte are required. (Operation preceeded by a start and ended with a stop). —Write one to 8 bytes to the Clock/Control Registers with the desired clock, or control data. This sequence starts with a start bit, requires a slave byte of “11011110” and an address within the CCR and is terminated by a stop bit. A write to the CCR changes EEPROM values so these initiate a nonvolatile write cycle and will take up to 10ms to complete. Writes to undefined areas have no effect. The RWEL bit is reset by the completion of a nonvolatile write write cycle, so the sequence must be repeated to again ini- tiate another change to the CCR contents. If the sequence is not completed for any reason (by send- ing an incorrect number of bits or sending a start instead of a stop, for example) the RWEL bit is not reset and the device remains in an active mode. —Writing all zeros to the status register resets both the WEL and RWEL bits. —A read operation occurring between any of the previ- ous operations will not interrupt the register write operation. —The RWEL and WEL bits can be reset by writing a 0 to the Status Register. Protected Addresses X1240 Array Lock 0 0 0 None None 0 0 1 600h - 7FFh Upper 1/4 0 1 0 400h - 7FFh Upper 1/2 0 1 1 000h - 7FFh Full Array 1 0 0 000h - 03Fh First Page 1 0 1 000h - 07Fh First 2 pgs 1 1 0 000h - 0FFh First 4 pgs 1 1 1 000h - 1FFh First 8 Pgs |
Số phần tương tự - X1240 |
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Mô tả tương tự - X1240 |
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