ST162552 datasheet(7/28 Pages) EXAR

tên linh kiện	ST162552

Giải thích chi tiết về linh kiện	DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER WITH FIFOs

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ST16C2552

FIFO POLLED MODE OPERATION

When FCR BIT-0=1; resetting IER BIT 3-0 to zero puts

the ST16C2552 in the FIFO polled mode of operation.

Since the receiver and transmitter are controlled

separately either one or both can be in the polled mode

operation by utilizing the Line Status Register.

A) LSR BIT-0 will be set as long as there is one byte

in the receive FIFO.

B) LSR BIT4-1 will specify which error(s) has oc-

curred.

C) LSR BIT-5 will indicate when the transmit FIFO is

empty.

D) LSR BIT-6 will indicate when both transmit FIFO

and transmit shift register are empty.

E) LSR BIT-7 will indicate when there are any errors

in the receive FIFO.

PROGRAMMABLE BAUD RATE GENERATOR

Each UART section of the ST16C2552 contains a

programmable Baud Rate Generator that is capable

of taking any clock input from DC-24 MHz and dividing

it by any divisor from 1 to 216 -1. The output frequency

of the Baudout* is equal to 16X of transmission baud

rate (Baudout*=16 x Baud Rate). Customize Baud

Rates can be achieved by selecting proper divisor

values for MSB and LSB of baud rate generator.

INTERRUPT ENABLE REGISTER (IER)

The Interrupt Enable Register (IER) masks the incom-

ing interrupts from receiver ready, transmitter empty,

line status and modem status registers to the INT

output pin.

IER BIT-0:

0=disable the receiver ready interrupt.

1=enable the receiver ready interrupt.

REGISTER FUNCTIONAL DESCRIPTIONS

TRANSMIT AND RECEIVE HOLDING REGISTER

The serial transmitter section consists of a Transmit

Hold Register (THR) and

Transmit Shift Register

(TSR). The status of the transmit hold register is

provided in the Line Status Register (LSR). Writing to

this register (THR) will transfer the contents of data

bus (D7-D0) to the Transmit holding register when-

ever the transmitter holding register or transmitter

shift register is empty. The transmit holding register

empty flag will be set to “1” when the transmitter is

empty or data is transferred to the transmit shift

register. Note that a write operation should be per-

formed when the transmit holding register empty flag

is set.

On the falling edge of the start bit, the receiver internal

counter will start to count 7 1/2 clocks (16x clock)

which is the center of the start bit. The start bit is valid

if the RX is still low at the mid-bit sample of the start

bit. Verifying the start bit prevents the receiver from

assembling a false data character due to a low going

noise spike on the RX input. Receiver status codes will

be posted in the Line Status Register.

FIFO INTERRUPT MODE OPERATION

When the receive FIFO (FCR BIT-0=1) and receive

interrupts (IER BIT-0=1) are enabled, receiver inter-

rupt will occur as follows:

A) The receive data available interrupts will be issued

to the CPU when the FIFO has reached its pro-

grammed trigger level; it will be cleared as soon as the

FIFO drops below its programmed trigger level.

B) The ISR receive data available indication also

occurs when the FIFO trigger level is reached, and like

the interrupt it is cleared when the FIFO drops below

the trigger level.

C) The data ready bit (LSR BIT-0) is set as soon as a

character is transferred from the shift register to the

receiver FIFO. It is reset when the FIFO is empty.

Số phần tương tự - ST162552

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