33394

2

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

Figure 1. 33394DH – Simplified Block Diagram and Typical Application

CAN

Wakeup

Logic

Band Gap

Reference

Standby

Control

VREF1

5.0 V

100 mA

LDO

T–Lim, I–Lim

VPP

5.0 V/3.3 V

150 mA

LDO

T–Lim, I–Lim

VDD3_3

3.3 V

120 mA

LDO, Pass

T–Lim, I–Lim

VDDL Drive

Adj. Volt.

40 mA

Dual Pass

T–Lim

Reset

Detection

VDDH,

VDD3_3,

VDDL

VDDH

5.0 V

400 mA

LDO

T–Lim, I–Lim

VREF2

5.0 V

100 mA

LDO

T–Lim, I–Lim

VREF3

5.0 V

100 mA

LDO

T–Lim, I–Lim

16 Bit

SPI

Control

Fault Rep.

POR Timer

Sleep

21

22

23

24

25

High–Speed CAN

Transceiver

20

19

18

+

10 nF

47

mF

+

10 nF

1.0

mF

+

10 nF

1.0

mF

10 nF

+

1.0

mF

10 nF

+

47

mF

17

16

15

14

13

12

11

10

VSEN

VBAT Volt.

125 mA

T–Lim, I–Lim

VKAM

Keep–Alive

Adj. Volt.

60 mA

I–Lim

GND

CANL

CANTXD

CANH

CANRXD

26

27

28

29

30

31

10 nF

10 nF

+

22

mF

2.6 V

+

100

mF

+

10

mF

Buck

Control

Logic

Boost

VPRE

Q3

MJD31C

Q2

MJD31C

10 nF

+

47

mF

10 nF

+

VDDH

5.0 V

CANRXD

42–44

41

BOOT

High–Side

Drive

Low–Side

Drive

Oscillator

Feed

Forward

Ramp

Generator

+

–

–

+

+

–

+

C1

100

mF

Enable

Sleep

32

33

34

35

36

37

10 k

10 k

10 k

110R

100R

VDDL

2.6 V

3.3 V

47

mF

VREF1

VPP_EN

VPP

VDD3_3

VDD3_FB

VDDL_B

DO

SCLK

DI

CS

/SLEEP

VREF3

VREF2

VDDH

5.0 V

5.0 V

5.0 V

47 k

HRT

/PRERESET

/HRESET

/PORESET

VDDL_X

VDDL_FB

5.0 V

5.0 V/3.3 V

9

WAKEUP

8

REGON

7

VSEN

38

39

40

5

VKAM

6

VKAM_FB

4

VIGN

3

KA_VBAT

1, 2

VBAT

4.7 k

ON

OFF

Control

Dp2

Dp1

To Q3

Cf1

Cf2

Lf1

6.8

mH

+

–

Vbg

11.7 k

40 k

Cc1

D2

VPRE_S

VPRE

VCOMP

100 pF

INV

GND

SW2G

SW1

Cb

100 nF

D1

Q1

MTD20N03HDL

L1

47

mH

Cc2

1.0 nF

Rc2

100 k

Cc3

3.3 nF

Rc3

430R

VPRE

5.6 V

22 k

20 k

VQ3

VKAM

2.6 V

Vbg

Notes: 1. In this configuration the device can operate with a minimum input voltage VBAT of 4.0 V (voltage at 33394 VBAT pins).

120 R

1.0

mF