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ADC31RF80IRMP bảng dữ liệu(PDF) 6 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  3-GSPS Telecom Receiver and Feedback Device
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6
ADC31RF80
SBAS860 – AUGUST 2017
www.ti.com
Product Folder Links: ADC31RF80
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
(1)
Full-scale signal is applied to the analog input; see the Power Consumption in Different Modes section for more details.
(2)
When used in dc-coupling mode, the common-mode voltage at the analog inputs should be kept within VCM ±25 mV for best
performance.
(3)
See Figure 79.
6.5 Electrical Characteristics
typical values are specified at an ambient temperature of 25°C; minimum and maximum values are specified over an ambient
temperature range of –40°C to +85°C; and chip sampling rate = 2949.12 MSPS, 50% clock duty cycle, DDC-bypassed
performance, AVDD19 = 1.9 V, AVDD = 1.15 V, DVDD = 1.15 V, –2-dBFS differential input, and 0-dB digital gain (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER CONSUMPTION (Divide-by-4, Complex Output Mode(1))
IAVDD19
1.9-V analog supply current
fS = 2949.12 MSPS
956
1439
mA
IAVDD
1.15-V analog supply current
fS = 2949.12 MSPS
499
813
mA
IDVDD
1.15-V digital supply current
fS = 2949.12 MSPS
975
1164
mA
PD
Power dissipation
fS = 2949.12 MSPS
3.51
4.71
W
Global power-down power
dissipation
245
mW
ANALOG INPUTS
Resolution
14
Bits
Differential input full-scale
1.35
VPP
VIC
Input common-mode voltage
1.2(2)
V
RIN
Input resistance
Differential resistance at dc
65
Ω
CIN
Input capacitance
Differential capacitance at dc
2
pF
VCM common-mode voltage output
1.2
V
Analog input bandwidth
(–3-dB point)
ADC driven with 50-Ω source
3200
MHz
CLOCK INPUT(3)
Input clock frequency
1.5
3
GSPS
Differential (peak-to-peak) input
clock amplitude
0.5
1.5
2.5
VPP
Input clock duty cycle
45%
50%
55%
Internal clock biasing
1.0
V
Internal clock termination
(differential)
100
Ω


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