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ADCS9888 bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện ADCS9888
Giải thích chi tiết về linh kiện  205/170/140 MSPS Video Analog Front End
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Pin Descriptions
Pin
Label
Type
Description
Analog Video Inputs
5R
AIN0
Analog
Input
Channel 0 Red (V) Video Input. Input for Red component video channel or
V chrominance channel in YUV/YPbPr/YCbCr applications. A high
impedance analog input. Input signal should be capacitively coupled to the
input using a 0.1 µF capacitor to support clamping and DC restoration.
Signal range of 0.5 V
PP to 1.0 VPP depending on gain setting.
13
G
AIN0
Analog
Input
Channel 0 Green (Y) Video Input. Input for Green component video
channel or Y luminance channel in YUV/YPbPr/YCbCr applications. A high
impedance analog input. Input signal should be capacitively coupled to the
input using a 0.1 µF capacitor to support clamping and DC restoration.
Signal range of 0.5 V
PP to 1.0 VPP depending on gain setting.
20
B
AIN0
Analog
Input
Channel 0 Blue (U) Video Input. Input for Blue component video channel
or U chrominance channel in YUV/YPbPr/YCbCr applications. A high
impedance analog input. Input signal should be capacitively coupled to the
input using a 0.1 µF capacitor to support clamping and DC restoration.
Signal range of 0.5 V
PP to 1.0 VPP depending on gain setting.
8R
AIN1
Analog
Input
Channel 1 Red (V) Video Input. See R
AIN0 for more information.
17
G
AIN1
Analog
Input
Channel 1 Green (Y) Video Input. See G
AIN0 for more information.
23
B
AIN1
Analog
Input
Channel 1 Blue (U) Video Input. See B
AIN0 for more information.
Analog Video Sync
12
SOGIN0
Analog
Input
Channel 0 Sync-On-Green-Input. A high impedance analog input. The
video channel containing synchronization information should be
capacitively coupled to this input using a 1.0 nF capacitor to support
negative peak clamping of the signal. When unused, this input should be
left unconnected.
16
SOGIN1
Analog
Input
Channel 1 Sync-On-Green-Input. See SOGIN0 for more information.
Sync/Clock Inputs
45
HSYNC0
Digital Input Channel 0 Horizontal Sync Input. A logic level synchronization signal at the
horizontal line rate is applied to this input. In applications where a
composite, logic level sync signal is present, that signal should be
connected to the HSYNC input. A Schmitt trigger input is used for
improved noise rejection. See the applications section for more
information.
44
VSYNC0
Digital Input Channel 0 Vertical Sync Input. A logic level synchronization signal at the
vertical frame rate is applied to this input. A Schmitt trigger input is used
for improved noise rejection. See the applications section for more
information.
43
HSYNC1
Digital Input Channel 1 Horizontal Sync Input. See HSYNC0 for more information.
42
VSYNC1
Digital Input Channel 1 Vertical Sync Input. See VSYNC0 for more information.
30
CLAMP
Digital Input External CLAMP Timing Input. When enabled via Register OFh, Bit 7, this
input will turn on the clamp circuits in the analog video inputs. This signal
should be asserted during the black reference portion of the video
waveform. Please refer to the applications section for more information.
www.national.com
4


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