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FIN1216MTD bảng dữ liệu(PDF) 9 Page - Fairchild Semiconductor |
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FIN1216MTD bảng dữ liệu(HTML) 9 Page - Fairchild Semiconductor |
9 / 17 page 9 www.fairchildsemi.com Receiver AC Electrical Characteristics Over supply voltage and operating temperatures, unless otherwise specified Note 17: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. Note 18: Total channel latency from serializer to deserializer is (T + t TCCD) + (2*T + tRCCD). There is the clock period. Symbol Parameter Test Conditions Min Typ Max Units tRCOL RxCLKOut LOW Time 10.0 11.0 ns tRCOH RxCLKOut HIGH Time See Figure 8 10.0 12.2 ns tRSRC RxOut Valid Prior to RxCLKOut (Rising Edge Strobe) 6.5 11.6 ns tRHRC RxOut Valid After RxCLKOut (f = 40 MHz) 6.0 11.6 ns tRCOP Receiver Clock Output (RxCLKOut) Period 15.0 T 50.0 ns tRCOL RxCLKOut LOW Time See Figure 8 5.0 7.8 9.0 ns tRCOH RxCLKOut HIGH Time (Rising Edge Strobe) 5.0 7.3 9.0 ns tRSRC RxOut Valid Prior to RxCLKOut (f = 65 MHz) 4.5 7.7 ns tRHRC RxOut Valid After RxCLKOut 4.0 8.4 ns tRCOP Receiver Clock Output (RxCLKOut) Period 11.76 T 50.0 ns tRCOL RxCLKOut LOW Time See Figure 8 4.0 6.3 6.0 ns tRCOH RxCLKOut HIGH Time (Rising Edge Strobe) 4.5 5.4 6.5 ns tRSRC RxOut Valid Prior to RxCLKOut (f = 85 MHz) (FIN1218 only) 3.5 6.3 ns tRHRC RxOut Valid After RxCLKOut 3.5 6.5 ns tROLH Output Rise Time (20% to 80%) CL = 8 pF 2.2 5.0 ns tROHL Output Fall Time (80% to 20%) See Figure 5 2.1 5.0 ns tRCCD Receiver Clock Input to Clock Output Delay See Figure 10 (Note 18) 3.5 6.9 7.5 ns TA = 25°C and VCC = 3.3V tRPDD Receiver Power-Down Delay See Figure 14 1.0 µs tRSPB0 Receiver Input Strobe Position of Bit 0 1.0 2.15 ns tRSPB1 Receiver Input Strobe Position of Bit 1 4.5 5.8 ns tRSPB2 Receiver Input Strobe Position of Bit 2 See Figure 17 8.1 9.15 ns tRSPB3 Receiver Input Strobe Position of Bit 3 (f = 40 MHz) 11.6 12.6 ns tRSPB4 Receiver Input Strobe Position of Bit 4 15.1 16.3 ns tRSPB5 Receiver Input Strobe Position of Bit 5 18.8 19.9 ns tRSPB6 Receiver Input Strobe Position of Bit 6 22.5 23.6 ns tRSPB0 Receiver Input Strobe Position of Bit 0 0.7 1.4 ns tRSPB1 Receiver Input Strobe Position of Bit 1 2.9 3.6 ns tRSPB2 Receiver Input Strobe Position of Bit 2 See Figure 17 5.1 5.8 ns tRSPB3 Receiver Input Strobe Position of Bit 3 (f = 65 MHz) 7.3 8.0 ns tRSPB4 Receiver Input Strobe Position of Bit 4 9.5 10.2 ns tRSPB5 Receiver Input Strobe Position of Bit 5 11.7 12.4 ns tRSPB6 Receiver Input Strobe Position of Bit 6 13.9 14.6 ns tRSPB0 Receiver Input Strobe Position of Bit 0 0.49 1.19 ns tRSPB1 Receiver Input Strobe Position of Bit 1 2.17 2.87 ns tRSPB2 Receiver Input Strobe Position of Bit 2 3.85 4.55 ns tRSPB3 Receiver Input Strobe Position of Bit 3 See Figure 17 5.53 6.23 ns tRSPB4 Receiver Input Strobe Position of Bit 4 (f = 85 MHz) (FIN1218 only) 7.21 7.91 ns tRSPB5 Receiver Input Strobe Position of Bit 5 8.89 9.59 ns tRSPB6 Receiver Input Strobe Position of Bit 6 10.57 11.27 ns tRSKM RxIn Skew Margin f = 40 MHz; See Figure 18 490 ps (Note 17) f = 65 MHz; See Figure 18 400 f = 85 MHz (FIN1218 only); 252 See Figure 18 tRPLLS Receiver Phase Lock Loop Set Time See Figure 12 10.0 ms |
Số phần tương tự - FIN1216MTD |
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Mô tả tương tự - FIN1216MTD |
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