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AM24LC21INA bảng dữ liệu(PDF) 5 Page - List of Unclassifed Manufacturers |
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AM24LC21INA bảng dữ liệu(HTML) 5 Page - List of Unclassifed Manufacturers |
5 / 13 page AM24LC21 Dual Mode, 1K-bits (128 x 8) 2-Wire Serial EEPROM (Preliminary) Anachip Corp. www.anachip.com.tw Rev 0.0 Aug 10, 2002 5/13 Functional description 1.0 Overview The AM24LC21 operates in two modes, the transmit-only mode and the bi-directional mode. There is a separate two wire protocol to support each mode, each having a separate clock input and sharing a common data line (SDA). The device enters the Transmit-Only Mode upon power-up. In this mode, the device transmits data bits on the SDA pin in response to a clock signal on the VCLK pin. The device will remain in this mode until a valid high to low transition is placed on the SCL input. When a valid transition on SCL is recognized, the device will switch into the bi-directional mode. The only way to switch the device back to the transmit-only mode is to remove power from the device. 2.1 Transmit-only mode The device will power up in the transmit-only mode. This mode supports a unidirectional two wire protocol for trans-mission of the contents of the memory array. This device requires that it be initialized prior to valid data being sent in the transmit-only mode (see Initialization Procedure, below). In this mode, data is transmitted on the SDA pin in 8 bit bytes, each followed by a ninth, null bit (see Figure 2-1). The clock source for the transmit-only mode is provided on the VCLK pin, and a data bit is output on the rising edge on this pin. The eight bits in each byte are transmitted most significant bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory array is transmitted, the output will wrap around to the first location and continue. The bi-directional mode clock (SCL) pin must be held high for the device to remain in the transmit-only mode. 2.2 Initialization procedure After VCC has stabilized, the device will be in the transmit-only mode. Nine clock cycles on the VCLK pin must be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high impedance state. On the rising edge of the tenth clock cycle, the device will output the first valid data bit which will be the most significant bit of a byte. The device will power up at an indeterminate byte address. (Figure 2-2). SCL SDA VCLK T VHIGH T VLOW T VAA T VAA B IT1(LSB) N ULL BIT B IT7 B IT8(MSB) Figure 2-1. Transmit only mode SCL SDA VCLK V CC T VAA T VAA B IT8BIT7 11 10 9 8 2 1 T VPU H IGH IMPEDANCE FOR 9 CLOCK CYCLES Figure 2-2. Device initialization |
Số phần tương tự - AM24LC21INA |
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Mô tả tương tự - AM24LC21INA |
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