công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
STK1743-D45 bảng dữ liệu(PDF) 9 Page - List of Unclassifed Manufacturers |
|
STK1743-D45 bảng dữ liệu(HTML) 9 Page - List of Unclassifed Manufacturers |
9 / 10 page STK1743 March 1999 7-9 1. Read address 0000 (hex) Valid READ 2. Read address 1555 (hex) Valid READ 3. Read address 0AAA (hex) Valid READ 4. Read address 1FFF (hex) Valid READ 5. Read address 10F0 (hex) Valid READ 6. Read address 0F0E (hex) Initiate RECALL cycle Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvola- tile information is transferred into the SRAM cells. After the t RECALL cycle time the SRAM will once again be ready for READ and WRITE operations. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times. Note that the RTC registers are not affected by nonvolatile operations. AutoStoreTM OPERATION The STK1743 uses capacitance built into the mod- ule to perform an automatic STORE on power down. In order to prevent unnecessary STORE operations, automatic STOREs will be ignored unless at least one WRITE operation has taken place since the most recent STORE or RECALL cycle. Software- initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. POWER-UP RECALL During power up, or after any low-power condition (V CC < V RESET), an internal recall request will be latched. When V CC once again exceeds VSWITCH, a RECALL cycle will automatically be initiated and will take t RESTORE to complete. HARDWARE PROTECT The STK1743 offers hardware protection against inadvertent STORE and SRAM WRITE operation dur- ing low-voltage conditions. When V CC < VSWITCH, all software STORE operations and SRAM writes are inhibited. LOW AVERAGE ACTIVE POWER The STK1743 draws significantly less current when it is cycled at times longer than 50ns. Figure 2 shows the relationship between I CC and READ cycle time. Worst-case current consumption is shown for both CMOS and TTL input levels (commercial tem- perature range, V CC = 5.5V, 100% duty cycle on chip enable). Figure 3 shows the same relationship for WRITE cycles. If the chip enable duty cycle is less than 100%, only standby current is drawn when the chip is disabled. The overall average current drawn by the STK1743 depends on the following items: 1) CMOS vs. TTL input levels; 2) the duty cycle of chip enable; 3) the overall cycle rate for accesses; 4) the ratio of READs to WRITEs; 5) the operating temperature; 6) the V CC level; and 7) I/O loading. Figure 2: ICC (max) Reads 0 20 40 60 80 100 50 100 150 200 Cycle Time (ns) TTL CMOS Figure 3: ICC (max) Writes 0 20 40 60 80 100 50 100 150 200 Cycle Time (ns) TTL CMOS |
Số phần tương tự - STK1743-D45 |
|
Mô tả tương tự - STK1743-D45 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |