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AD9895 bảng dữ liệu(PDF) 8 Page - Analog Devices |
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AD9895 bảng dữ liệu(HTML) 8 Page - Analog Devices |
8 / 58 page REV. A –8– AD9891/AD9895 AD9895 PIN CONFIGURATION A B C D E F G H J K AD9895 TOP VIEW (Not to Scale) 1234 567 9 10 8 A1 CORNER INDEX AREA PIN FUNCTION DESCRIPTIONS 1 Pin Mnemonic Type 2 Description K9 VSG5 DO CCD Sensor Gate Pulse 5 J9 VSG6DO CCD Sensor Gate Pulse 6 K10 VSG7DO CCD Sensor Gate Pulse 7 J10 VSG8 DO CCD Sensor Gate Pulse 8 H10 H1 DO CCD Horizontal Clock 1 H9 H2 DO CCD Horizontal Clock 2 G10 HVDD P H1–H4 Driver Supply G9 HVSS P H1–H4 Driver Ground F10 H3 DO CCD Horizontal Clock 3 F9 H4 DO CCD Horizontal Clock 4 E10 RGVDD P RG Driver Supply E9 RGVSS P RG Driver Ground D9 RG DO CCD Reset Gate Clock D10 CLO DO Reference Clock Output for Crystal C10 CLI DI Reference Clock Input B10 TCVDD P Analog Supply for Timing Core C9 TCVSS P Analog Ground for Timing Core A10 AVDD1 P Analog Supply for AFE B9 AVSS1 P Analog Ground for AFE A9 BYP1 AO Analog Circuit Bypass B8 BYP2 AO Analog Circuit Bypass A8 CCDIN AI CCD Signal Input A7 BYP3 AO Analog Circuit Bypass B7 AVDD2 P Analog Supply for AFE B6 AVSS2 P Analog Ground for AFE A6 REFB AO Voltage Reference Bottom Bypass A5 REFT AO Voltage Reference Top Bypass B5 SL DI 3-Wire Serial Load Pulse A4 SDI DI 3-Wire Serial Data Input B4 SCK DI 3-Wire Serial Clock A3 MSHUT DO Mechanical Shutter Pulse B3 STROBE DO Strobe Pulse B2 DVSS P Digital Ground A2 DVDD P Digital Supply for VSG, V1–V4, HD, VD, MSHUT, STROBE, and Serial Interface NOTES 1See Figure 50 for circuit configuration. 2AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, P = Power. 3In Register Readback Mode 4In Frame Transfer CCD Mode Pin Mnemonic Type 2 Description A1 VD DO Vertical Sync Pulse (Input for Slave Mode, Output for Master Mode) B1 HD DO Horizontal Sync Pulse (Input for Slave Mode, Output for Master Mode) C1 SYNCDIExternal System Sync Input C2 LD/FD DO Line or Field Designator Output D1 DCLK DO Data Clock Output D2 CLPOB/ DO CLPOB or PBLK Output PBLK E2 DO DO Data Output (LSB) E1 D1 DO Data Output F2 D2/SDO DO Data Output (also Serial Data Output 3) F1 D3 DO Data Output G2 D4 DO Data Output G1 D5 DO Data Output H2 D6 DO Data Output H1 D7 DO Data Output J2 D8 DO Data Output J1 D9 DO Data Output K2 D10 DO Data Output K1 D11 DO Data Output (MSB) K3 DRVDD P Data Output Driver Supply K4 DRVSS P Data Output Driver Ground J3 VSUB DO CCD Substrate Bias J4 SUBCK DO CCD Substrate Clock (E-Shutter) K5 V1 DO CCD Vertical Transfer Clock 1 J5 V2 DO CCD Vertical Transfer Clock 2 K6 V3 DO CCD Vertical Transfer Clock 3 J6 V4 DO CCD Vertical Transfer Clock 4 K7 VSG1/V5DO CCD Sensor Gate Pulse 1 (also V5 4) J7 VSG2/V6DO CCD Sensor Gate Pulse 2 (also V64) K8 VSG3/V7DO CCD Sensor Gate Pulse 3 (also V7 4) J8 VSG4/V8DO CCD Sensor Gate Pulse 4 (also V8 4) |
Số phần tương tự - AD9895 |
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Mô tả tương tự - AD9895 |
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