PACDN004, SZPACDN004

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5

the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be

slightly higher than the maximum supply voltage.

As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected

Array as possible, with minimum PCB trace lengths to the power supply, ground planes and between the signal input and the

ESD device to minimize stray series inductance.

Additional Information

See also ON Semiconductor Application Notes AP209, “Design Considerations for ESD Protection” and AP219, “ESD

Protection for USB 2.0 Systems”.

POSITIVE SUPPLY RAIL

CHANNEL

INPUT

GROUND RAIL

CHASSIS GROUND

SYSTEM OR

CIRCUITRY

BEING

PROTECTED

LINE BEING

PROTECTED

ONE

CHANNEL

OF

PACDN004

0.22

mF

0 A

20 A

Figure 2. Application of Positive ESD Pulse between Input Channel and Ground