NBSG16M datasheet(3/12 Pages) ONSEMI

tên linh kiện	NBSG16M

Giải thích chi tiết về linh kiện	2.5V/3.3V Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer

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NBSG16M

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3

50

W

50

W

VTD

D

VTD

Q

VBB

VEE

VCC

50

W

50

W

Figure 2. Logic Diagram

Q

VCC

16 mA

50

W

50

W

Figure 3. CML Output Structure

VEE

Table 2. Interfacing Options

INTERFACING OPTIONS

CONNECTIONS

CML

Connect VTD and VTD to VCC

LVDS

Connect VTD and VTD together

AC−COUPLED

Bias VTD and VTD Inputs within (VIHCMR)

Common Mode Range

RSECL, PECL, NECL

Standard ECL Termination Techniques

LVTTL, LVCMOS

An external voltage should be applied to the

unused complimentary differential input.

Nominal voltage 1.5 V for LVTTL and VCC/2 for

LVCMOS inputs.

Table 3. ATTRIBUTES

Characteristics

Value

ESD Protection

Human Body Model

Machine Model

Charged Device Model

> 1 kV

> 100 V

> 4 kV

Moisture Sensitivity (Note 4)

Level 1

Flammability Rating

Oxygen Index: 28 to 34

UL 94 V−0 @ 0.125 in

Transistor Count

145

Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

4. For additional Moisture Sensitivity information, refer to Application Note AND8003/D.

Số phần tương tự - NBSG16M

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
ON Semiconductor	NBSG16M	149Kb / 11P	2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer April, 2006 ??Rev. 5
	NBSG16M	143Kb / 12P	Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer June, 2014 ??Rev. 9
	NBSG16MMN	149Kb / 11P	2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer April, 2006 ??Rev. 5
	NBSG16MMNG	149Kb / 11P	2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer April, 2006 ??Rev. 5
	NBSG16MMNG	143Kb / 12P	Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer June, 2014 ??Rev. 9

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Mô tả tương tự - NBSG16M

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
ON Semiconductor	NBSG16M	143Kb / 12P	Multilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer June, 2014 ??Rev. 9
	NB6L16	117Kb / 12P	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/Driver/Translator Buffer September, 2004 ??Rev. 4
	NB6L16	188Kb / 12P	2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL Clock or Data Receiver/ Driver/Translator Buffer March, 2007 ??Rev. 6
	NB4L16M	919Kb / 12P	2.5V/3.3V, 5 Gb/s Multi Level Clock/Data Input to CML Driver / Receiver / Buffer / Translator with Internal Termination February, 2006 ??Rev. 1
	NBSG16M	149Kb / 11P	2.5 V/3.3 VMultilevel Input to CML Clock/Data Receiver/Driver/Translator Buffer April, 2006 ??Rev. 5
	NB6L11	114Kb / 12P	2.5V / 3.3V MULTILEVEL INPUT TO DIFFERENTIAL LVPECL/LVNECL 1:2 CLOCK OR DATA FANOUT BUFFER / TRANSLATOR April, 2004 ??Rev. 2
	NB4N316M	159Kb / 12P	Receiver to CML Driver/Translator with Input Hysteresis July, 2016 ??Rev. 6
	NB4N11M	223Kb / 11P	3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator November, 2005 ??Rev. 1
	NB7V585M	156Kb / 8P	1.8V / 2.5V Differential 2:1 Mux Input to 1:6 CML Clock/Data Fanout Buffer/Translator February, 2009 ??Rev. 1
	NB6L572M	161Kb / 9P	2.5V / 3.3V Differential 4:1 Mux to 1:2 CML Clock/Data Fanout / Translator November, 2009 ??Rev. 1

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