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932SQL456AGILFT bảng dữ liệu(PDF) 11 Page - Integrated Device Technology

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Giải thích chi tiết về linh kiện  Low-Power CK420BQ Derivative for PCIe Separate Clock Architectures
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nhà sản xuất  IDT [Integrated Device Technology]
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REVISION B 09/29/15
11
LOW-POWER CK420BQ DERIVATIVE FOR PCIE SEPARATE CLOCK ARCHITECTURES
932SQL456 DATASHEET
DC Electrical Characteristics–CPU, SRC, NS_SAS, NS_SRC, DOT96 LP-HCSL
Outputs
Electrical Characteristics–48MHz
TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Slew rate
dV/dt
Scope averaging on
2
3.3
4.5
V/ns
1, 2, 3
Slew rate matching
∆dV/dt
Slew rate matching, Scope
averaging on
11.1
20
%
1, 2, 4
Rise/Fall Time Matching
∆Trf
Rise/fall matching, Scope
averaging off
9.0
125
ps
1, 8, 9
Voltage High
VHigh
660
845
850
Voltage Low
VLow
-150
122
150
Max Voltage
Vmax
1026
1150
1, 7
Min Voltage
Vmin
-300
-22
1, 7
Crossing Voltage (abs)
Vcross_abs
Scope averaging off
250
482
550
mV
1, 5
Crossing Voltage (var)
∆-Vcross
Scope averaging off
22
140
mV
1, 6
2 Measured from differential waveform
7 Includes overshoot and undershoot.
8 Measured from single-ended waveform
9 Measured with scope averaging off, using statistics function. Variation is difference between min and max.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window
centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the
voltage thresholds the oscilloscope is to use for the edge rate calculations.
Statistical measurement on
single-ended signal using
oscilloscope math function.
(Scope averaging on)
mV
Measurement on single ended
signal using absolute value.
mV
1Guaranteed by design and characterization, not 100% tested in production. Z
O=85Ω (differential impedance).
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window
around differential 0V.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential
rising edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max
(V_cross absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than
TA = TAMB; Supply Voltage VDDx = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Output High Voltage
VOH
IOH = -1 mA
2.4
V
Output Low Voltage
VOL
IOL = 1 mA
0.55
V
Clock High Time
THIGH
1.5V
8.094
10.036
ns
1
Clock Low Time
TLOW
1.5V
7.694
9.836
ns
1
Edge Rate
tslewr/f_USB
Rising/Falling edge rate
1
1.7
2
V/ns
1,2
Duty Cycle
dt1
VT = 1.5 V
45
50.4
55
%
1
Jitter, Cycle to cycle
tjcyc-cyc
VT = 1.5 V
29
250
ps
1
See "Power Supply and Test Loads" page for termination circuits
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured between 0.8V and 2.0V


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