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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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TP3094V bảng dữ liệu(PDF) 5 Page - National Semiconductor (TI) |
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TP3094V bảng dữ liệu(HTML) 5 Page - National Semiconductor (TI) |
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5 / 19 page  5 www.national.com When both the transmit and receive frame sync of a channel are missing the channel will go into Power Down Mode (if only one of them is missing the channel will not go into Power Down). A max- imum of 32 frame sync pulses must be missing for power down and the channel will achieve its reset state after 32.5us. The channel will recover from power down, within the time of 4ms after the frame syncs (transmit or receive) will be active. When the device is in 32-bit mode, missing FSX0, FSR0 for 512us, will force all channels in power down mode. When the master clock MCLK is missing, all the channels will go into the Global Power Down Mode, with the lowest possible power consump- tion. The device will recover from this mode, when the clock signal comes back (and at least one frame sync is present), and then the active channels will operate after less than 100ms. The device will go into the same Global Power Down Mode when all the frame syncs (of all the channels, in case of 8bit mode, the FSX0, FSR0 in case of 32-bit mode) are not present or when all 4 PDN signals are active. The recovery time from this mode for the first active channel is less than 100ms. Transmit Section The transmit section input is an operational ampli- fier, with provision for gain adjustment using two external resistors. Only the inverting input is pro- vided (together with the output), this allows, be- side the adjustment of the gain, to implement the echo balance function with external passive com- ponents. The opamp drives the antialiasing input filter, fol- lowed by the A to D converter, which provides the digital input to the signal processing unit. The signal processing unit accepts the signal samples from each channel input stage, performs the necessary decimation and filtering function, PCM compression and provides the eight bit samples to the PCM interface block. The analog input is dc biased at the value of 2.4V. A DC decoupling is necessary between this input and the SLIC output. The maximum analog signal level, at the op-amp output, is 1.12Vrms. Maximum recommended transmit gain is 20dB (10x). Receive Section This section takes the 8 bit samples from the PCM interface block and performs all the signal processing functions, such as PCM expansion according to the ALaw or uLaw and signal filter- ing. Then, for each channel it drives the Digital to Analog converter, through the proper interpola- tion stages and filters. Finally the signal is filtered and buffered to the output receive pin. The maxi- mum output level voltage on the VRO pins on a load of 5kOhm+100pF is 1.12Vrms. PCM Interface The PCM interface consists of the following sig- nals • DX, DR - transmit and receive digital signals, carrying the pcm samples • FSX0-3, FSR0-3 - transmit and receive frame signals • TSX - output time slots signal, indicating the time slot occupied on the DX by the device • PCMMode - PCM interface select • A/uLaw - A-law/ u-law select signal • TABLE 1. A/uLaw Coding • MCLK - bit clock signal MCLK is both the system master clock and the PCM bus bit clock, and it is selected internally to be either 8.192MHz, 4.096MHz, 2.048MHz, or 1.536/ 1.544MHz. The internal clock selection is perfomed, based on the relative ratio between the frame signals (FS) and the clock signals. For proper functional- ity all the channel FS must have the same valid rate of 8kHz (giving a valid clock rate). In case one of the frame syncs runs other than 8kHz, the device will not function properly. Each bit on DX is clocked out on the rising edges of the bit clock (MCLK), starting from the Most Significant Bit (Sign bit). Each bit on DR is clocked in on the falling edges of the bit clock, starting from the MSB. The device may operate on to the PCM bus in two modes, selected by the input pin PCMMode; when PCMMode is “0V” the 8bit mode is selected and when PCMMode is “+5V” the 32-bit mode is selected. PCMMode = HIGH PCMMode = LOW 32 bit 8 bit A/uLaw = HIGH A/uLaw = LOW A-law u-law |
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