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AD9886KS-140 bảng dữ liệu(PDF) 9 Page - Analog Devices |
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9 / 32 page REV. 0 AD9886 –9– Power Supply VD Main Power Supply These pins supply power to the main ele- ments of the circuit. It should be as quiet and filtered as possible. VDD Digital Output Power Supply A large number of output pins (up to 52) switching at high speed (up to 140 MHz) generates a lot of power supply transients (noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize output noise trans- ferred into the sensitive analog circuitry. If the AD9886 is interfacing with lower- voltage logic, VDD may be connected to a lower supply voltage (as low as 2.5 V) for compatibility. PVD Clock Generator Power Supply The most sensitive portion of the AD9886 is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide “quiet,” noise-free power to these pins. GND Ground The ground return for all circuitry on chip. It is recommended that the AD9886 be assembled on a single solid ground plane, with careful attention to ground current paths. Serial Port (Two-Wire) SDA Serial Port Data I/O SCL Serial Port Data Clock A0 Serial Port Address Input 1 A1 Serial Port Address Input 2 For a full description of the 2-wire serial regis- ter and how it works, refer to the Control Register section. SCAN Function SCANIN Data Input for SCAN Function Data can be loaded serially into the 48-bit SCAN register through this pin, clocking it in with the SCANCLK pin. It then comes out of the 48 data outputs in parallel. This function is useful for loading known data into a graph- ics controller chip for testing purposes. SCANOUT Data Output for SCAN Function The data in the 48-bit SCAN register can be read through this pin. Data is read on a FIFO basis and is clocked via the SCANCLK pin. SCANCLK Data Clock for SCAN Function This pin clocks the data through the SCAN register. It controls both data input and data output. |
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