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STM32F103xx bảng dữ liệu(PDF) 10 Page - STMicroelectronics

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STM32F103xx bảng dữ liệu(HTML) 10 Page - STMicroelectronics

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ARM® 32-bit Cortex®-M3 limitations
STM32F10xx8 STM32F10xxB
10/41
DocID14574 Rev 13
1.1.6
SVC and BusFault/MemManage may occur out of order
Description
If an SVC exception is generated by executing the SVC instruction while the following
instruction fetch is faulted, then the MemManage or BusFault handler may be entered even
though the faulted instruction which followed the SVC should not have been executed.
Workaround
A workaround is only required if the SVC handler will not return to the return address that
has been stacked for the SVC exception and the instruction access after the SVC will fault.
If this is the case then padding can be inserted between the SVC and the faulting area of
code, for example, by inserting NOP instructions.


Số phần tương tự - STM32F103xx

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STMicroelectronics
STM32F103XX STMICROELECTRONICS-STM32F103XX Datasheet
12Mb / 1134P
   STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm-based 32-bit MCUs
December 2018 Rev 20
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Mô tả tương tự - STM32F103xx

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