STM32F101xx datasheet(9/41 Pages) STMICROELECTRONICS

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STM32F10xx8 STM32F10xxB

ARM® 32-bit Cortex®-M3 limitations

Workaround

If the DFSR register does not have any bit set when the debug monitor is entered, this

means that we must be in this “corner case” and so, that a BKPT instruction was executed

in debug monitor mode.

1.1.4

Cortex-M3 may freeze for SLEEPONEXIT single instruction ISR

Description

If the Cortex-M3 SLEEPONEXIT functionality is used and the concerned interrupt service

routine (ISR) contains only a single instruction, the core becomes frozen. This freezing may

occur if only one interrupt is active and it is preempted by an interrupt whose handler only

contains a single instruction.

However, any new interrupt that causes a preemption would cause the core to become

unfrozen and behave correctly again.

Workaround

This scenario does not happen in real application systems since all enabled ISRs should at

least contain one instruction. Therefore, if an empty ISR is used, then insert an NOP or any

other instruction before the exit instruction (BX or BLX).

1.1.5

Interrupted loads to SP can cause erroneous behavior

Description

If an interrupt occurs during the data-phase of a single word load to the stack-pointer

(SP/R13), erroneous behavior can occur. In all cases, returning from the interrupt will result

in the load instruction being executed an additional time. For all instructions performing an

update to the base register, the base register will be erroneously updated on each

execution, resulting in the stack-pointer being loaded from an incorrect memory location.

The affected instructions are:

1.

LDR SP,[Rn],#imm

2.

LDR SP,[Rn,#imm]!

3.

LDR SP,[Rn,#imm]

4.

LDR SP,[Rn]

5.

LDR SP,[Rn,Rm]

Workaround

As of today, there is no compiler generating these particular instructions. This limitation can

only occur with hand-written assembly code.

Both issues may be worked around by replacing the direct load to the stack-pointer, with an

intermediate load to a general-purpose register followed by a move to the stack-pointer.

Example: the following instruction "LDR SP, [R0]" can be replaced by

“LDR R2,[R0]

MOV SP,R2 "

Số phần tương tự - STM32F101xx

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
STMicroelectronics	STM32F101XX	12Mb / 1134P	STM32F101xx, STM32F102xx, STM32F103xx, STM32F105xx and STM32F107xx advanced Arm-based 32-bit MCUs December 2018 Rev 20

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Mô tả tương tự - STM32F101xx

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