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TS68EN360MR33L bảng dữ liệu(PDF) 2 Page - ATMEL Corporation |
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TS68EN360MR33L bảng dữ liệu(HTML) 2 Page - ATMEL Corporation |
2 / 82 page 2 TS68EN360 2113A–HIREL–03/02 Introduction QUICC Architecture Overview The QUICC is 32-bit controller that is an extension of other members of the TS68300 family. Like other members of the TS68300 family, the QUICC incorporates the inter- module bus (IMB). The TS68302 is an exception, having an 68000 bus on chip. The IMB provides a common interface for all modules of the TS68300 family, which allows the development of new devices more quickly by using the library of existing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to implement this option. The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in Figure 1. Figure 1. QUICC Block Diagram R suffix PGA 241 Ceramic Pin Grid Array Cavity Up A suffix CERQUAD 240 Ceramic Leaded Chip Carrier Cavity Down EXTERNAL BUS INTERFACE SYSTEM PROTECTION SIM 60 CPU32+ CORE IMB (32 BIT) RISC CONTROLLER SYSTEM I/F 2.5-KBYTE DUAL-PORT RAM DRAM CONTROLLER AND CHIP SELECTS CPM PERIODIC TIMER CLOCK GENERATION OTHER FEATURES BREAKPOINT LOGIC JTAG COMMUNICATIONS PROCESSOR FOUR GENERAL- PURPOSE TIMERS INTERRUPT CONTROLLER OTHER FEATURES TIMER SLOT ASSIGNER SEVEN SERIAL CHANNELS TWO IDMAs FOURTEEN SERIAL DMAs |
Số phần tương tự - TS68EN360MR33L |
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