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SM320F2812-EP bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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3 / 172 page TMS320F2810, TMS320F2811, TMS320F2812 TMS320C2810, TMS320C2811, TMS320C2812 www.ti.com SPRS174T – APRIL 2001 – REVISED MAY 2012 4.1 32-Bit CPU-Timers 0/1/2 ................................................................................................. 55 4.2 Event Manager Modules (EVA, EVB) ................................................................................... 58 4.2.1 General-Purpose (GP) Timers ................................................................................ 61 4.2.2 Full-Compare Units ............................................................................................. 61 4.2.3 Programmable Deadband Generator ........................................................................ 61 4.2.4 PWM Waveform Generation .................................................................................. 61 4.2.5 Double Update PWM Mode ................................................................................... 61 4.2.6 PWM Characteristics ........................................................................................... 62 4.2.7 Capture Unit ..................................................................................................... 62 4.2.8 Quadrature-Encoder Pulse (QEP) Circuit ................................................................... 62 4.2.9 External ADC Start-of-Conversion ........................................................................... 62 4.3 Enhanced Analog-to-Digital Converter (ADC) Module ............................................................... 63 4.4 Enhanced Controller Area Network (eCAN) Module .................................................................. 68 4.5 Multichannel Buffered Serial Port (McBSP) Module .................................................................. 73 4.6 Serial Communications Interface (SCI) Module ....................................................................... 77 4.7 Serial Peripheral Interface (SPI) Module ............................................................................... 80 4.8 GPIO MUX ................................................................................................................. 83 5 Development Support ........................................................................................................ 86 5.1 Device and Development Support Tool Nomenclature ............................................................... 86 5.2 Documentation Support .................................................................................................. 87 5.3 Community Resources .................................................................................................... 89 6 Electrical Specifications ..................................................................................................... 91 6.1 Absolute Maximum Ratings .............................................................................................. 91 6.2 Recommended Operating Conditions .................................................................................. 91 6.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) ............. 92 6.4 Current Consumption ..................................................................................................... 93 6.5 Current Consumption Graphs ............................................................................................ 95 6.6 Reducing Current Consumption ......................................................................................... 97 6.7 Emulator Connection Without Signal Buffering for the DSP ......................................................... 97 6.8 Power Sequencing Requirements ....................................................................................... 98 6.9 Signal Transition Levels ................................................................................................. 100 6.10 Timing Parameter Symbology .......................................................................................... 101 6.11 General Notes on Timing Parameters ................................................................................ 101 6.12 Test Load Circuit ......................................................................................................... 101 6.13 Device Clock Table ...................................................................................................... 102 6.14 Clock Requirements and Characteristics ............................................................................. 103 6.14.1 Input Clock Requirements ................................................................................... 103 6.14.2 Output Clock Characteristics ................................................................................ 104 6.15 Reset Timing ............................................................................................................. 104 6.16 Low-Power Mode Wakeup Timing ..................................................................................... 108 6.17 Event Manager Interface ................................................................................................ 112 6.17.1 PWM Timing ................................................................................................... 112 6.17.2 Interrupt Timing ................................................................................................ 114 6.18 General-Purpose Input/Output (GPIO) – Output Timing ............................................................ 115 6.19 General-Purpose Input/Output (GPIO) – Input Timing .............................................................. 116 6.20 Serial Peripheral Interface (SPI) Master Mode Timing .............................................................. 117 6.21 Serial Peripheral Interface (SPI) Slave Mode Timing ............................................................... 122 6.22 External Interface (XINTF) Timing ..................................................................................... 126 6.23 XINTF Signal Alignment to XCLKOUT ................................................................................ 130 6.24 External Interface Read Timing ........................................................................................ 131 6.25 External Interface Write Timing ........................................................................................ 133 6.26 External Interface Ready-on-Read Timing With One External Wait State ....................................... 134 6.27 External Interface Ready-on-Write Timing With One External Wait State ....................................... 137 Copyright © 2001–2012, Texas Instruments Incorporated Contents 3 |
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