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RZTHC6748 bảng dữ liệu(PDF) 1 Page - Texas Instruments |
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RZTHC6748 bảng dữ liệu(HTML) 1 Page - Texas Instruments |
1 / 273 page Product Folder Order Now Technical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TMS320C6748 SPRS590G – JUNE 2009 – REVISED JANUARY 2017 TMS320C6748™ Fixed- and Floating-Point DSP 1 Device Overview 1 1.1 Features 1 • 375- and 456-MHz C674x Fixed- and Floating- Point VLIW DSP • C674x Instruction Set Features – Superset of the C67x+ and C64x+ ISAs – Up to 3648 MIPS and 2746 MFLOPS – Byte-Addressable (8-, 16-, 32-, and 64-Bit Data) – 8-Bit Overflow Protection – Bit-Field Extract, Set, Clear – Normalization, Saturation, Bit-Counting – Compact 16-Bit Instructions • C674x Two-Level Cache Memory Architecture – 32KB of L1P Program RAM/Cache – 32KB of L1D Data RAM/Cache – 256KB of L2 Unified Mapped RAM/Cache – Flexible RAM/Cache Partition (L1 and L2) • Enhanced Direct Memory Access Controller 3 (EDMA3): – 2 Channel Controllers – 3 Transfer Controllers – 64 Independent DMA Channels – 16 Quick DMA Channels – Programmable Transfer Burst Size • TMS320C674x Floating-Point VLIW DSP Core – Load-Store Architecture With Nonaligned Support – 64 General-Purpose Registers (32-Bit) – Six ALU (32- and 40-Bit) Functional Units – Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point – Supports up to Four SP Additions Per Clock, Four DP Additions Every Two Clocks – Supports up to Two Floating-Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle – Two Multiply Functional Units: – Mixed-Precision IEEE Floating-Point Multiply Supported up to: – 2 SP × SP → SP Per Clock – 2 SP × SP → DP Every Two Clocks – 2 SP × DP → DP Every Three Clocks – 2 DP × DP → DP Every Four Clocks – Fixed-Point Multiply Supports Two 32 × 32- Bit Multiplies, Four 16 × 16-Bit Multiplies, or Eight 8 × 8-Bit Multiplies per Clock Cycle, and Complex Multiples – Instruction Packing Reduces Code Size – All Instructions Conditional – Hardware Support for Modulo Loop Operation – Protected Mode Operation – Exceptions Support for Error Detection and Program Redirection • Software Support – TI DSP BIOS™ – Chip Support Library and DSP Library • 128KB of RAM Shared Memory • 1.8-V or 3.3-V LVCMOS I/Os (Except for USB and DDR2 Interfaces) • Two External Memory Interfaces: – EMIFA – NOR (8- or 16-Bit-Wide Data) – NAND (8- or 16-Bit-Wide Data) – 16-Bit SDRAM With 128-MB Address Space – DDR2/Mobile DDR Memory Controller With one of the Following: – 16-Bit DDR2 SDRAM With 256-MB Address Space – 16-Bit mDDR SDRAM With 256-MB Address Space • Three Configurable 16550-Type UART Modules: – With Modem Control Signals – 16-Byte FIFO – 16x or 13x Oversampling Option • LCD Controller • Two Serial Peripheral Interfaces (SPIs) Each With Multiple Chip Selects • Two Multimedia Card (MMC)/Secure Digital (SD) Card Interfaces With Secure Data I/O (SDIO) Interfaces • Two Master and Slave Inter-Integrated Circuits (I2C Bus™) |
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