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TMP102AIDRLTG4 bảng dữ liệu(PDF) 5 Page - Texas Instruments |
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TMP102AIDRLTG4 bảng dữ liệu(HTML) 5 Page - Texas Instruments |
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5 / 30 page  TMP102 www.ti.com SBOS397F – AUGUST 2007 – REVISED DECEMBER 2015 Electrical Characteristics (continued) At TA = 25°C and VS = 1.4 to 3.6 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT POWER SUPPLY Operating supply range +1.4 +3.6 V Serial bus inactive, CR1 = 1, CR0 = 7 10 0 (default) Serial bus active, SCL frequency = IQ Average quiescent current 15 μA 400 kHz Serial bus active, SCL frequency = 85 3.4 MHz Serial bus inactive 0.5 1 Serial bus active, SCL frequency = 10 ISD Shutdown current 400 kHz μA Serial bus active, SCL frequency = 80 3.4 MHz TEMPERATURE Specified range –40 125 °C Operating range –55 150 °C 6.6 Timing Requirements See the Timing Diagrams section for additional information. FAST MODE HIGH-SPEED MODE UNIT MIN TYP MAX MIN TYP MAX ƒ(SCL) SCL operating frequency V+ 0.001 0.4 0.001 2.85 MHz Bus-free time between STOP and t(BUF) 600 160 ns START condition Hold time after repeated START condition. t(HDSTA) 600 160 ns After this period, the first clock is generated. See Figure 7 t(SUSTA) repeated start condition setup time 600 160 ns t(SUSTO) STOP condition setup time 600 160 ns t(HDDAT) Data hold time 100 900 25 105 ns t(SUDAT) Data setup time 100 25 ns t(LOW) SCL-clock low period V+ , see Figure 7 1300 210 ns t(HIGH) SCL-clock high period See Figure 7 600 60 ns tFD Data fall time See Figure 7 300 80 ns See Figure 7 300 ns tRD Data rise time SCLK ≤ 100 kHz, 1000 ns see Figure 7 tFC Clock fall time See Figure 7 300 40 ns tRC Clock rise time See Figure 7 300 40 ns Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: TMP102 |
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