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TMP102AIDRLR bảng dữ liệu(PDF) 3 Page - Texas Instruments |
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TMP102AIDRLR bảng dữ liệu(HTML) 3 Page - Texas Instruments |
3 / 30 page 1 2 3 6 5 4 SDA V+ ADD0 SCL GND ALERT TMP102 www.ti.com SBOS397F – AUGUST 2007 – REVISED DECEMBER 2015 5 Pin Configuration and Functions DRL Package 6-Pin SOT563 Top View Pin Functions PIN I/O DESCRIPTION NO. NAME 1 SCL I Serial clock. Open-drain output; requires a pullup resistor. 2 GND — Ground 3 ALERT O Overtemperature alert. Open-drain output; requires a pullup resistor. 4 ADD0 I Address select. Connect to GND or V+ 5 V+ I Supply voltage, 1.4 V to 3.6 V 6 SDA I/O Serial data. Open-drain output; requires a pullup resistor. 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT Supply Voltage 4 V Input Voltage(2) –0.5 3.6 V Output voltage 3.6 V Operating temperature –55 150 °C Junction temperature 150 °C Storage temperature, Tstg –60 150 °C (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. (2) Input voltage rating applies to all TMP102 input voltages. 6.2 Handling Ratings VALUE UNIT Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000 V Machine model (MM) ±200 (1) Level listed above is the passing level per ANSI, ESDA, and JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Copyright © 2007–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: TMP102 |
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