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STGAP1S bảng dữ liệu(PDF) 7 Page - STMicroelectronics

tên linh kiện STGAP1S
Giải thích chi tiết về linh kiện  gapDRIVE?? galvanically isolated single gate driver
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STGAP1S
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67
List of figures
Figure 1.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 2.
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3.
Low voltage section 3.3 V voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 4.
High voltage section 3.3 V voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 5.
HW cross conduction prevention in half-bridge configuration with two single gate
drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 6.
Transitions causing the DT generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7.
Synchronous control signal edges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8.
Control edges signal overlapped, example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 9.
Control edges signal overlapped, example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 10.
Control edges signal not overlapped and outside DT (direct control) . . . . . . . . . . . . . . . . . 28
Figure 11.
DESAT protection timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 12.
Example of VCE active clamping protection connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 13.
VCECLAMP timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 14.
Example of short turn-on pulses when 2LTO occurs at each cycle . . . . . . . . . . . . . . . . . . 34
Figure 15.
Example of short turn-off pulse when 2LTO occurs at each cycle . . . . . . . . . . . . . . . . . . . 34
Figure 16.
Example of operation with 2LTO in “Fault” mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 17.
Gate paths check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 18.
SENSE comparator and resistor check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19.
DESAT comparator check circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 20.
SPI timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 21.
SPI daisy chain connection example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 22.
SPI daisy chain connection example when bootstrap technique is used for high-side
drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 23.
Block diagram of the CRC generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 24.
Typical application diagram in half-bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 25.
SO24W package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 26.
SO24W suggested land pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65


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