SN74SSTV32852

24-BIT TO 48-BIT REGISTERED BUFFER

WITH SSTL_2 INPUTS AND OUTPUTS

SCES361C – AUGUST 2001 – REVISED FEBRUARY 2003

1

POST OFFICE BOX 655303

Widebus

 Family

DIMMs

Specifications

RESET Input

Receivers, Resets All Registers, and

Forces All Outputs Low

JESD 78, Class II

– 2000-V Human-Body Model (A114-A)

– 1000-V Charged-Device Model (C101)

description/ordering information

All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are SSTL_2, Class II compatible.

The SN74SSTV32852 operates from a differential clock (CLK and CLK). Data are registered at the crossing

of CLK going high and CLK going low.

The device supports low-power standby operation. When RESET is low, the differential input receivers are

RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must

be held at a valid logic high or low level.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in

the low state during power up.

ORDERING INFORMATION

TA

PACKAGE†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

0

°C to 70°C

LFBGA – GKF

Tape and reel

SN74SSTV32852GKFR

SV852

† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Copyright

 2003, Texas Instruments Incorporated

Widebus is a trademark of Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.