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ADC12D1620LGMLS bảng dữ liệu(PDF) 4 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  12-Bit, Single Or Dual, 3200- or 1600-MSPS RF Sampling Analog-to-Digital Converter (ADC)
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ADC12D1620LGMLS bảng dữ liệu(HTML) 4 Page - Texas Instruments

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VA
A GND
-
+
100:
100:
VA
AGND
VA
AGND
100
VBIAS
50k
50k
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AGND
VA
AGND
100
VA
AGND
VA
AGND
100
VBIAS
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4
ADC12D1620QML-SP
SNAS717 – APRIL 2017
www.ti.com
Product Folder Links: ADC12D1620QML-SP
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Pin Functions: Analog Front-End and Clock Pins
PIN
TYPE
DESCRIPTION
EQUIVALENT CIRCUIT
NAME
NO.
ANALOG FRONT-END AND CLOCK PINS
CLK+
CLK–
U2/V1
I
Differential converter sampling clock. In the non-
DES mode, the analog inputs are sampled on the
positive transitions of this clock signal. In the DES
mode, the selected input is sampled on both
transitions of this clock. This clock must be AC-
coupled.
DCLK_RST+
DCLK_RST–
V2/W1
I
Differential DCLK reset. A positive pulse on this
input is used to reset the DCLKI and DCLKQ
outputs of two or more ADC12D1620 devices in
order to synchronize them with other ADC12D1620
devices in the system. DCLKI and DCLKQ are
always in phase with each other, unless one
channel is powered down, and do not require a
pulse from DCLK_RST to become synchronized.
The pulse applied here must meet timing
relationships with respect to the CLK input. Although
supported, this feature has been superseded by
AutoSync.
RCLK+
RCLK–
Y4/W5
I
Reference clock input. When the AutoSync feature
is active, and the ADC12D1620 is in slave mode,
the internal divided clocks are synchronized with
respect to this input clock. The delay on this clock
may be adjusted when synchronizing multiple ADCs.
This feature is available in ECM with the DRC bits of
the AutoSync Control Register (Addr: Eh, Bits:
15:7).
RCOut1+,
RCOut1–
RCOut2+,
RCOut2–
Y5/U6
V6/V7
O
Reference clock output 1 and 2. These signals,
when enabled, provide a reference clock. The
RCOut rates for all of the available modes can be
found in Table 8; the rates displayed in the table are
independent of whether the ADC is in master or
slave mode. RCOut1 and RCOut2 are used to drive
the RCLK of ADC12D1620 to enable automatic
synchronization for multiple ADCs (AutoSync
feature). The impedance of each trace from RCOut1
and RCOut2 to the RCLK of ADC12D1620 should
be 100-Ω differential. Having two clock outputs
allows the auto-synchronization to propagate as a
binary tree. Use the DOC bit of the AutoSync
Control Register (Addr: Eh; Bit: 1) to enable or
disable this feature; default is disabled.


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Texas Instruments
ADC12D1620LGMLS TI-ADC12D1620LGMLS Datasheet
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Mô tả tương tự - ADC12D1620LGMLS

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