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ADC12D1620CCMLS bảng dữ liệu(PDF) 8 Page - Texas Instruments |
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ADC12D1620CCMLS bảng dữ liệu(HTML) 8 Page - Texas Instruments |
8 / 82 page GND VA 100 k: GND VA 100 k: GND VA 100 k: GND VA 50 k: GND VA 8 ADC12D1620QML-SP SNAS717 – APRIL 2017 www.ti.com Product Folder Links: ADC12D1620QML-SP Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated Pin Functions: Analog Front-End and Clock Pins (continued) PIN TYPE DESCRIPTION EQUIVALENT CIRCUIT NAME NO. NDM A5 I Non-demuxed mode select. Setting this input to logic-high causes the digital output bus to be in the 1:1 non-demuxed mode. Setting this input to logic- low causes the digital output bus to be in the 1:2 demuxed mode. This feature is pin-controlled only and remains active during both ECM and non-ECM. PDI PDQ U3 V3 I Power down I and Q channels. Setting either input to logic-high powers down the respective I or Q channel. Setting either input to logic-low brings the respective I or Q channel to a operational state after a finite time delay. This pin is active in both ECM and non-ECM. In ECM, each pin is logically OR'd with its respective bit. Therefore, either this pin or the PDI and PDQ bits in the Configuration Register (Addr: 0h; Bit: 11 and Bit: 10, respectively) can be used to power down the I and Q channels. RSV W3 — Reserved. This pin is used for internal purposes and must be connected to GND through a 100-kΩ resistor. NONE RSV1 E3 — Decouple this pin with a 100-nF capacitor with a low resistance, low inductance path to GND. NONE RSV2 F4 — Decouple this pin with a 100-nF capacitor with a low resistance, low inductance path to GND. NONE SCLK C5 I Serial clock. In ECM, serial data is shifted into and out of the device synchronously to this clock signal. This clock may be disabled and held logic-low, as long as timing specifications are not violated when the clock is enabled or disabled. SCS C4 I Serial chip select. In ECM, when this signal is asserted (logic-low), SCLK is used to clock in serial data that is present on SDI and to source serial data on SDO. When this signal is de-asserted (logic- high), SDI is ignored and SDO is tri-state. SDI B4 I Serial data-in. In ECM, serial data is shifted into the device on this pin while SCS signal is asserted (logic-low). |
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