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AD5450YUJ bảng dữ liệu(PDF) 2 Page - Analog Devices |
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2 / 16 page –2– REV. PrD AD5450/AD5451/AD5452/AD5453–SPECIFICATIONS1 PRELIMINARY TECHNICAL DATA Parameter Min Typ M a x Units Conditions STATIC PERFORMANCE AD5450 Resolution 8 Bits Relative Accuracy ±0.25 L S B Differential Nonlinearity ± ½ L S B Guaranteed Monotonic AD5451 Resolution 1 0 Bits Relative Accuracy ±0.25 L S B Differential Nonlinearity ± ½ L S B Guaranteed Monotonic AD5452 Resolution 1 2 Bits Relative Accuracy ±0.5 L S B Differential Nonlinearity ± ½ L S B Guaranteed Monotonic AD5453 Resolution 1 4 Bits Relative Accuracy ± 2 L S B Differential Nonlinearity ± 1 L S B Guaranteed Monotonic Total Unadjusted Error ±2.44 m V Gain Error ±1.22 m V Gain Error Temp Coefficient 2 ±5 ppm FSR/°C Output Leakage Current ± 1 0 n A Data = 0000H, TA = 25°C, IOUT1 ± 5 0 n A Data = 0000H, IOUT1 Output Voltage Compliance Range 1.23 V REFERENCE INPUT 2 Reference Input Range ± 1 0 V VREF Input Resistance 8 9 . 3 1 2 k Ω Input resistance TC = -50ppm/°C DIGITAL INPUTS 2 Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V 1.7 V VDD = 2.5 V to 3.6 V Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V 0.7 V VDD = 2.5 V to 2.7 V Input Leakage Current, IIL 1 µ A Input Capacitance 1 0 p F DYNAMIC PERFORMANCE 2 Reference Multiplying BW 10 MHz VREF = +/-3.5V, DAC loaded all 1s Output Voltage Settling Time VREF = 10V, RLOAD = 100Ω, CLOAD = 15pF DAC latch alternately loaded with 0s and 1s. AD5450 1 0 0 n s Measured to +/-16mV of FS AD5451 1 1 0 n s Measured to +/-4mV of FS AD5452 1 6 0 n s Measured to +/-1mV of FS AD5453 1 8 0 n s Measured to +/-1mV of FS Digital Delay 2 0 4 0 n s Interface delay time 10% to 90% Dettling Time 1 0 3 0 n s Rise and Fall time, VREF = 10V, RLOAD = 100 Ω, C LOAD = 15pF Digital to Analog Glitch Impulse 3 nV-s 1 LSB change around Major Carry, VREF=0V Multiplying Feedthrough Error DAC latch loaded with all 0s. - 7 5 d B Reference = 1MHz. Reference = 10MHz. Output Capacitance IOUT1 5 p F DAC Latches Loaded with all 0s 1 0 p F DAC Latches Loaded with all 1s IOUT2 1 0 p F DAC Latches Loaded with all 0s 5 p F DAC Latches Loaded with all 1s Digital Feedthrough 0 . 1 nV-s Feedthrough to DAC output with CS high and Alternate Loading of all 0s and all 1s. (VDD = 2.5 V to 5.5 V, VREF = +10 V, IOUTx = O V. All specifications TMIN to TMAX unless otherwise noted. DC performance measured with OP1177, AC performance with AD9631 unless otherwise noted.) |
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