CHARGE PUMP

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

ICP

o-source

Main and Auxiliary Charge

Pump Output Current (Note 4)

VCP

1.0

mA

ICP

o-sink

VCP

−1.0

mA

ICP

o-source

VCP

4.0

mA

ICP

o-sink

VCP

−4.0

mA

ICP

o-TRI

Current

0.5

≤ VCP

−2.5

0.1

2.5

nA

ICP

ICP

o-source

CP Sink vs Source Mismatch

VCP

310

%

ICP

VCP

o

CP Current vs Voltage

0.5

≤ VCP

815

%

ICP

CP Current vs Temperature

VCP

8

%

DIGITAL INTERFACE (DATA, CLOCK, LE)

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

V

IH

High-Level Input Voltage

Vµc = 1.72V to 5.5V

0.8 Vµc

V

V

IL

Low-Level Input Voltage

Vµc = 1.72V to 5.5V

0.2 Vµc

V

I

IH

High-Level Input Current

V

−1.0

1.0

µA

I

IL

Low-Level Input Current

V

−1.0

1.0

µA

V

OL

Low-Level Output Current

I

5)

0.1

0.4

V

MICROWIRE TIMING

Value

Unit

Symbol

Parameter

Conditions

Min

Typ

Max

t

CS

Data to Clock Setup Time

See Data Input Timing

50

ns

t

CH

Data to Clock Hold Time

See Data Input Timing

20

ns

t

CWH

Clock Pulse Width High

See Data Input Timing

50

ns

t

CWL

Clock Pulse Width Low

See Data Input Timing

50

ns

t

ES

Clock to Load Enable Setup

Time

See Data Input Timing

50

ns

t

EW

Load Enable Pulse Width

See Data Input Timing

50

ns

1.0 Functional Description

The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthesizer

such as the National Semiconductor LMX2370/2371/2372, a voltage controlled oscillator (VCO), and a passive loop filter. The fre-

quency synthesizer includes a phase detector, a current mode charge pump, as well as programmable reference [R] and feed-

back [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R-counter to

obtain a comparison reference frequency. This reference signal (

f

and compared with the feedback signal (

f

phase/frequency detector’s current source output pumps charge into the loop filter, which then integrates into the VCO’s control

voltage. The function of the phase/frequency comparator is to adjust the control voltage presented to the VCO until the feedback

signal frequency and phase match that of the reference signal. When this “Phase-Locked” condition exists, the VCO frequency

will be N times that of the comparison frequency, where N is the integer divide ratio.

1.1 REFERENCE OSCILLATOR INPUT

The reference oscillator frequency for the Main and Auxiliary PLLs is provided from the external reference through the OSC

OSC

R-counter. The input has a V

is connected to the output of a crystal oscillator.

1.2 REFERENCE DIVIDERS (R-COUNTERS)

The Main and Auxiliary R-counters are both clocked through the oscillator block in common. The maximum frequency is 50 MHz.

Both R-counters are CMOS design and 15-bit in length with programmable divider ratio from 2 to 32,767.

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