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LMX2355TM bảng dữ liệu(PDF) 10 Page - National Semiconductor (TI) |
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LMX2355TM bảng dữ liệu(HTML) 10 Page - National Semiconductor (TI) |
10 / 23 page Functional Description 1.0 GENERAL The basic phase-lock-loop (PLL) configuration consists of a high-stability crystal reference oscillator, a frequency synthe- sizer such as the National Semiconductor LMX2354, a volt- age controlled oscillator (VCO), and a passive loop filter. The frequency synthesizer includes a phase detector, current mode charge pump, as well as programmable reference [R] and feedback [N] frequency dividers. The VCO frequency is established by dividing the crystal reference signal down via the R counter to obtain a frequency that sets the comparison frequency. This reference signal, f r, is then presented to the input of a phase/frequency detector and compared with an- other signal, f p, the feedback signal, which was obtained by dividing the VCO frequency down by way of the N counter and fractional circuitry. The phase/frequency detector’s cur- rent source outputs pump charge into the loop filter, which then converts the charge into the VCO’s control voltage. The phase/frequency comparator’s function is to adjust the volt- age presented to the VCO until the feedback signal’s fre- quency (and phase) match that of the reference signal. When this ‘phase-locked’ condition exists, the RF VCO’s frequency will be N+F times that of the comparison fre- quency, where N is the integer divide ratio and F is the fractional component. The fractional synthesis allows the phase detector frequency to be increased while maintaining the same frequency step size for channel selection. The division value N is thereby reduced giving a lower phase noise referred to the phase detector input, and the compari- son frequency is increased allowing faster switching times. 1.1 REFERENCE OSCILLATOR INPUTS The reference oscillator frequency for the RF and IF PLLs is provided by an external reference through the OSC IF pin and OSC RF pin. OSCIF/OSCRF block can operate 50 MHz with an input sensitivity of 0.5 Vpp. The OSC bit (see program- ming description 4.1.1), selects whether the oscillator input pins OSC IF and OSCRF drive the IF and RF R counters separately or by a common input signal path. When an external TCXO is connected only at the OSC IF input pin and not at the OSC RF pin, the TCXO drives both IF R counter and RF R counter. When configured as separate inputs, the OSC IF pin drives the IF R counter while the OSCRF drives the RF R counter. The inputs have a V CC/2 input threshold and can be driven from an external CMOS or TTL logic gate. 1.2 REFERENCE DIVIDERS (R COUNTERS) The RF and IF R Counters are clocked through the oscillator block either separately or in common. The maximum fre- quency is 50 MHz. Both R Counters are 15-bit CMOS counters with a divide range from 3 to 32,767. (See program- ming description 4.1.3.) 1.3 PROGRAMMABLE DIVIDERS (N COUNTERS) The RF and IF N Counters are clocked by the small signal fin RF and fin IF input pins respectively. The RF N Counter can be configured as a fractional or fully integer counter. The LMX2354 RF N counter is 19 bits with 15 bits integer divide and 4 bits fractional. The integer part is configured as a 2-bit A Counter, a 2-bit B Counter and a 11-bit C Counter. The LMX2354 is capable of operating from 500 MHz to 1.2 GHz with the 8/9/12/13 prescaler offering a continuous integer divide range from 40 to 16,383 in fractional mode and 24 to 262143 in full integer mode. The LMX2354 is capable of operating from 1.2 GHz to 2.5 GHz with the 16/17/20/21 prescaler offering a continuous integer divide range from 80 to 32,767 in fractional mode and 48 to 52,4287 in full integer mode. The RF counters for the LMX2354 also contain frac- tional compensation, programmable in either 1/15 or 1/16 modes. The LMX2354 IF N counter is 15-bit integer divider configured with a 3-bit A Counter and a 12-bit B Counter offering a continuous integer divide range from 56 to 32,767 over the frequency range of 10 MHz to 550 MHz. The IF N counter does not include fractional compensation. The tables below show the differences between the LMX2354 in integer mode and in quadruple modulus prescaler with P = 16/17/20/21. Also, the tables show that the bit used for the lower modulus prescaler values is different between the LMX2350 and the LMX2354. For the LMX2350 bit N<9> =0 (MSB of the A Word) is used for the 16/17 modulus and for the LMX2354 bit N<8> =0 is used for the 8/9/12/13 modu- lus. So if the LMX2354 is replacing a LMX2350 then bits N<8> and N<9> need to be swapped. LMX2354 RF N Counter Register in Fractional Mode with P = 16/17/20/21: C Word B Word A Word Fractional Word N 19 18 17 16 15 14 13 12 11 10 987 6 5432 1 1–47 Divide ratios less than 48 are impossible since it is required that C ≥3 These bits are used for the fractional word when the part is operated in fractional mode 48–79 Some of these values are legal divide ratios, some are not 80* 000000 0 0 1 0100 0 0 81 000000 0 0 1 0100 0 1 ... 1056 000010 0 0 0 1000 0 0 ... ...... . . . .... . . 32,767 111111 1 1 1 1111 1 1 *Minimum continuous divide ratio is P •[MAX{A,B}+2] www.national.com 10 |
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