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LMX2313U bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI) |
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LMX2313U bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI) |
4 / 29 page Pin Descriptions (Continued) Pin Number Pin Name I/O Description I/O Circuit Configuration 11 NC — No Connect. 12 Data I High impedance CMOS Data input. Serial Data is entered MSB first. The last two bits are the address for the target registers. The Data is internally referenced to V µC. 13 LE I High impedance CMOS LE input. When Latch Enable goes HIGH, data stored in the 22-bit shift register is loaded into one the 3 control registers, based on the address field. The Latch Enable is internally referenced to V µC. 14 GND — Digital ground. 15 CE I High impedance CMOS Chip Enable input. Provides logical power-down control of the device. Pull-up to V µC if unused. The Chip Enable is internally referenced to V µC. 16 V µC — Power supply for MICROWIRE™ circuitry. Must be ≤ V CC. Typically connected to same supply level as microprocessor or baseband controller to enable programming at low voltages. 17 NC — No Connect. 18 V CC — Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors should be placed as close as possible to this pin and be connected directly to the ground plane. 19 FL O Fastlock mode output. In Fastlock mode this pin is at logic low. When not in Fastlock mode, this pin is in TRI-STATE mode. This pin can also be forced to TRI-STATE, forced low or forced high by the programming of the first two-bits of the Timeout Counter. 20 V P — Power supply for charge pump. Must be ≥ V CC. www.national.com 4 |
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