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MC14001BFEL bảng dữ liệu(PDF) 1 Page - ON Semiconductor |
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1 / 12 page © Semiconductor Components Industries, LLC, 2005 February, 2005 − Rev. 4 1 Publication Order Number: MC14001B/D MC14001B Series B−Suffix Series CMOS Gates MC14001B, MC14011B, MC14023B, MC14025B, MC14071B, MC14073B, MC14081B, MC14082B The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. Features • Supply Voltage Range = 3.0 Vdc to 18 Vdc • All Outputs Buffered • Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range. • Double Diode Protection on All Inputs Except: Triple Diode Protection on MC14011B and MC14081B • Pin−for−Pin Replacements for Corresponding CD4000 Series B Suffix Devices • Pb−Free Packages are Available* MAXIMUM RATINGS (Voltages Referenced to VSS) Symbol Parameter Value Unit VDD DC Supply Voltage Range − 0.5 to +18.0 V Vin, Vout Input or Output Voltage Range (DC or Transient) − 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient) per Pin ±10 mA PD Power Dissipation, per Package (Note 1) 500 mW TA Ambient Temperature Range − 55 to +125 °C Tstg Storage Temperature Range − 65 to +150 °C TL Lead Temperature (8−Second Soldering) 260 °C Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/ _C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high−impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Device Description DEVICE INFORMATION MC14001B Quad 2−Input NOR Gate MC14011B Quad 2−Input NAND Gate MC14023B Triple 3−Input NAND Gate MC14025B Triple 3−Input NOR Gate MC14071B Quad 2−Input OR Gate MARKING DIAGRAMS 1 14 PDIP−14 P SUFFIX CASE 646 MC140xxBCP AWLYYWW SOIC−14 D SUFFIX CASE 751A TSSOP−14 DT SUFFIX CASE 948G 1 14 140xxB AWLYWW 14 0xxB ALYW 1 14 xx = Specific Device Code A = Assembly Location WL, L = Wafer Lot YY, Y = Year WW, W = Work Week SOEIAJ−14 F SUFFIX CASE 965 1 14 MC140xxB AWLYWW MC14073B Triple 3−Input AND Gate MC14081B Quad 2−Input AND Gate MC14082B Dual 4−Input AND Gate See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet. ORDERING INFORMATION http://onsemi.com |
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