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STK17TA8-R45 bảng dữ liệu(PDF) 2 Page - List of Unclassifed Manufacturers |
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2 / 22 page STK17TA8 February 2004 2 Document Control # ML0023 rev 0.3 PACKAGES PIN DESCRIPTIONS Pin Name I/O Description A0 - A16 Input Address: The 17 address inputs select one of 131,072 bytes in the nvSRAM array or one of 16 bytes in the clock register map. DQ0 -DQ7 I/O Data: Bi-directional 8-bit data bus for accessing the nvSRAM array and clock. E Input Chip Enable: The active low E input selects the device. W Input Write Enable: The active low W enables data on the DQ pins to be written to the adddress location latched by the falling edge of E. G Input Output Enable: The active low G input enables the data output buffers during read cycles. Deasserting G high causes the DQ pins to tri-state. X1, X2 Input Crystal: Connections for 32.768 kHz crystal. Vrtccap Power Supply Capacitor supplied backup RTC supply voltage. Vrtcbat Power Supply Battery supplied backup RTC supply voltage. VCCX Power Supply Power (+ 3V) HSB I/O Hardware Store Busy (I/O) INT Output Interrupt Output: Can be programmed to respond to the clock alarm, the watchdog timer and the power monitor. Programmable to either active high (push/pull) or active low (open-drain). VCAP Power Supply Autostore Capacitor: Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements. VSS Power Supply Ground 48 Pin 300 mil SSOP 40 Pin 600 mil DIP (not to scale) |
Số phần tương tự - STK17TA8-R45 |
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Mô tả tương tự - STK17TA8-R45 |
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