REV. 0

–4–

AD5426/AD5432/AD5443

Parameter

3.0 V to 5.5 V

4.5 V to 5.5 V

Unit

Conditions/Comments

50

50

MHz max

Max clock frequency

20

20

ns min

SCLK cycle time

88

ns min

SCLK high time

88

ns min

SCLK low time

2

13

13

ns min

SYNC falling edge to SCLK active edge setup time

55

ns min

Data setup time

33

ns min

Data hold time

55

ns min

SYNC rising edge to SCLK active edge

30

30

ns min

Minimum

SYNC high time

3

80

45

ns typ

SCLK active edge to SDO valid

120

65

ns max

NOTES

°C to +125°C. Guaranteed by design and characterization, not subject to production test.

Specifications subject to change without notice.

DB15

DB0

SCLK

SYNC

DIN

ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF

SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.

Figure 1. Standalone Mode Timing Diagram

DB15 (N)

DB0 (N)

DB15

(N+1)

DB0 (N+1)

SCLK

SYNC

SDIN

SDO

ALTERNATiVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS

DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING

EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.

DB15(N)

DB0(N)

Figure 2. Daisy-chain and Readback Modes Timing Diagram