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LM9822CCWMX2 bảng dữ liệu(PDF) 8 Page - National Semiconductor (TI) |
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LM9822CCWMX2 bảng dữ liệu(HTML) 8 Page - National Semiconductor (TI) |
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8 / 22 page  8 www.national.com Pin Descriptions Connection Diagram Analog Power VA The two A pins are the analog supply pins. They should be connected to a voltage source of +5V and bypassed to AGND with a 0.1µF monolithic capacitor in parallel with a 10µF tantalum capacitor. AGND These two pins are the ground returns for the analog supplies. VD This is the positive supply pin for the digital I/O pins. It should be connected to a voltage source between +3.3V and +5.0V and be bypassed to DGND with a 0.1µF monolithic capacitor in parallel with a 10µF tantalum capacitor. DGND This is the ground return for the digital sup- ply. Analog Input/Output OSR, OSG, OSB Analog Inputs. These inputs (for Red, Green, and Blue) should be tied to the sen- sor’s OS (Output Signal) through DC block- ing capacitors. VREF+, VREFMID, VREF- Voltage reference bypass pins. VREF+, VREFMID, and VREF- should each be bypassed to AGND through a 0.1uF mono- lithic capacitor. Timing Control MCLK Master clock input. The ADC conversion rate will be 1/2 of MCLK. 12MHz is the max- imum frequency for MCLK. VSMP Sample timing input signal. If VSMP is high on the rising edge of MCLK, the input is sampled on the rising edge of the next MCLK. The reference signal for the next pixel will be sampled one to four MCLKs later, depending on the value in the CDSREF configuration bits. If CDS is not enabled, the internal reference will be sam- pled during the reference sample time. The number of MCLK cycles between VSMP pulses determines the pixel rate. Timing Diagrams 1 through 6 illustrate the VSMP timings for all the valid pixel rates. Note: See the applications section of the datasheet for the proper timing relationships between VSMP and MCLK. CLMP Clamp timing input. If CLMP and VSMP are high on the rising edge of MCLK, all three OS inputs will be internally connected to VCLAMP during the next pixel. VCLAMP is either VREF+ or VREF- depending on the state of the Signal Polarity bit in the Sample Mode register (Reg. 0, Bit 4). Data Output D7 -D0 Data Output pins. The 14 bit conversion results of the ADC are multiplexed in 8 bit bytes to D7-D0 synchronous with MCLK. The MSB consists of data bits d13-d6 on pins D7-D0 and the LSB consists of d5-d0 on pins D7-D3 with D1 and D0 low. Serial Input/Output SCLK Serial Shift Clock. Input data on SDI is valid on the rising edge of SCLK. The minimum SCLK period is 1 tMCLK. SDO Serial Data Output. Data bits are shifted out of SDO on falling edges of SCLK. The first eight falling edges of SCLK after SEN goes low will shift out eight data bits (MSB first) from the configuration register addressed during the previous SEN low time. SDI Serial Data Input. A read/write bit, followed by a four address bits and eight data bits is shifted into SDI, MSB first. Data should be valid on the rising edge of SCLK. If the read/write bit is a “0” (a write), then the shifted data bits will be stored. If the read/write bit is a “1” (a read), then the data bits will be ignored, and SDO will shift out the addressed register’s contents during the next SEN low time. SEN Shift enable and load signal. When SEN is low, data is shifted into SDI. When SEN goes high, the last thirteen bits (one read/write, four address and eight data) shifted into SDI will be used to program the addressed configuration register. SEN must be high for at least 3 MCLK cycles between SEN low times. LM9822 28 pin SOIC SCLK SDI SEN D2 D0 VD DGND D4 11 12 13 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 23 22 21 24 25 26 27 28 D7 D6 D5 MCLK VA VA VREF- OSB OSG CLMP OSR VREF+ AGND AGND VSMP SDO VREFMID VBANDGAP D3 D1 |
Số phần tương tự - LM9822CCWMX2 |
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Mô tả tương tự - LM9822CCWMX2 |
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