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LM9811CCVF bảng dữ liệu(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
tên linh kiện LM9811CCVF
Giải thích chi tiết về linh kiện  10-Bit Greyscale/30-Bit Color Linear CCD Sensor Processor
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nhà sản xuất  NSC [National Semiconductor (TI)]
Trang chủ  http://www.national.com
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LM9811CCVF bảng dữ liệu(HTML) 6 Page - National Semiconductor (TI)

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AC Electrical Characteristics, MCLK Dependent (Continued)
The following specifications apply for AGND = DGND = DGND
(I/O) = 0V, VA = VD = VD(I/O) = +5.0VDC, REF IN = +1.225VDC,
f
MCLK = 20MHz, tMCLK = 1/fMCLK,tr = tf = 5ns, Rs = 25Ω,CL(databus loading) = 50 pF/pin. Refer to Table 2. Configuration
Register Parameters for limits labelled C.R. Boldface limits apply for T
A = TJ = TMIN to TMAX; all other limits TA = TJ =
25˚C.
Symbol
Parameter
Conditions
Typical
Limits
Units
(Note 9)
(Note 10)
(Limits)
t
S/HREF
Falling Edge of
φ1 to Ref. Sample
Standard CCD Mode
C.R.
ns
Either Edge of
φ1 to Ref. Sample
Even/Odd CCD Mode
t
S/HSIG
Falling Edge of
φ1 to Sig. Sample
Standard CCD Mode
C.R.
ns
Either Edge of
φ1 to Sig. Sample
Even/Odd CCD Mode
t
S/HWIDTH
Sample Pulse Width
50ns
1
t
MCLK
(Acquisition Time)
t
SYNCLOW
SYNC Low Between Lines
100ns
2
t
MCLK (min)
t
B
SYNC Setup of
φ1 to End Line
2
t
MCLK (max)
t
CCLKWIDTH
CCLK Pulse Width
250ns
5
t
MCLK
t
DATAVALID
Data Valid Time from EOC Low
300
ns (min)
t
EOCWIDTH
EOC Pulse Width
250ns
5
t
MCLK
φ1 and φ2 Frequency
Standard CCD Mode
2.5MHz
f
MCLK/8
Hz
Even/Odd CCD Mode
1.25MHz
f
MCLK/16
Hz
φ1 and φ2 Duty Cycle
50
%
Electrical Characteristics (Notes)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test condi-
tions.
Note 2: All voltages are measured with respect to GND = AGND = DGND = DGND(I/O) = 0V, unless otherwise specified.
Note 3: When the input voltage (VIN) at any pin exceeds the power supplies (VIN < GND or VIN > VA or VD), the current at that pin should be limited to 25 mA.
The 50 mA maximum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25
mA to two.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, θJA and the ambient temperature, TA. The maximum
allowable power dissipation at any temperature is PD = (TJmax–TA)/θJA.TJmax = 150˚C for this device. The typical thermal resistance (θJA) of this part when board
mounted is 52˚C/W for the V52A PLCC package, and 70˚C/W for the VEG52A TQFP package.
Note 5: Human body model, 100pF capacitor discharged through a 1.5 k
Ω resistor.
Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any National Semiconductor
Linear Data Book for other methods of soldering surface mount devices.
Note 7: A Zener diode clamps the OS analog input to AGND as shown below. This input protection, in combination with the external clamp capacitor and the output
impedance of the CCD, prevents damage to the LM9811 from transients during power-up.
Note 8: To guarantee accuracy, it is required that VA and VD be connected together to the same power supply with separate bypass capacitors at each supply pin.
Note 9: Typicals are at TJ = TA = 25˚C, fMCLK = 20MHz, and represent most likely parametric norm.
Note 10: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
DS012813-4
www.national.com
6


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