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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional,

but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply

only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions.

imum package input current rating limits the number of pins that can simultaneously safely exceed the power supplies with an input current of 25mA to two.

is 52°C/W for the V52A PLCC package

.

Note 5: Human body model, 100pF capacitor discharged through a 1.5k

Ω resistor.

Note 6: See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National Semiconduc-

tor Linear Data Book for other methods of soldering surface mount devices.

Note 7: A Zener diode clamps the OS analog inputs to AGND as shown below. This input protection, in combination with the external clamp capacitor and the output

impedance of the sensor, prevents damage to the LM9812 from transients during power-up.

Note 10: Tested limits are guaranteed to National's AOQL (Average Outgoing Quality Level).

Note 11: Integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that best fits the actual transfer function of the ADC.

EOC low time

ns

EOC high time

ns

Read Phase = 0°)

Phase = 180°)

edge of EOC

ns (min)

(OCLK IN)

OCLK rising edge to EOC falling edge

(Gain Coefficient Write Phase = 0°),

OCLK falling edge to EOC falling edge

(Gain Coefficient Write Phase = 180°)

1 bus mode w/ext OCLK

ns (min)

ns (max)

(OCLK IN)

OCLK rising edge to EOC rising edge

(Gain Coefficient Write Phase = 0°),

OCLK falling edge to EOC rising edge

(Gain Coefficient Write Phase = 180°)

2 bus mode w/ext OCLK

40ns

ns (min)

ns (max)

(GCLK IN)

GCLK rising edge to EOC falling edge

(Gain Coefficient Write Phase = 0°),

GCLK falling edge to EOC falling edge

(Gain Coefficient Write Phase = 180°)

w/ext GCLK

40ns

ns (min)

ns (max)

Symbol

Parameter

Conditions

Typical

(Note 9)

Limits

(Note 10)

Units

(Limits)

To Internal

Circuitry

OS Input

AGND