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LM9617CCEA bảng dữ liệu(PDF) 4 Page - National Semiconductor (TI) |
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LM9617CCEA bảng dữ liệu(HTML) 4 Page - National Semiconductor (TI) |
4 / 37 page Confidential 4 www.national.com Pin Descriptions Pin Name I/O Typ Description 1 vsrvdd I0 P Analog bidirectional, it should be connect to ground via a 1.0 µf capacitor. This pin is the internal charge pump voltage source. 2 vrl I A Anti blooming pin. This pin is normally tied to ground. 3 vdd_pix I P 3.3 volt supply for the pixel array. 4 irq O D Digital output, the interrupt request pin. This pin generates interrupts during snapshot mode. 5 sadr I D Digital input with pull down resistor. This pin is used to program different slave addresses for the sensor in an I 2C compatible system. 6 sda IO D I 2C compatible serial interface data bus. The output stage of this pin has an open drain driver. 7 sclk I D I2C compatible serial interface clock. 8 snapshot I D Digital input with pull down resistor used to activate (trigger) a snapshot sequence. 9 resetb I D Digital input with pull up resistor. When forced to a logic 0 the sensor is reset to its default power up state. The resetb signal is internally synchronized to mclk which must be run- ning for a reset to occur. 10 pdwn I D Digital input with pull down resistor. When forced to a logic 1 the sensor is put into power down mode. 11 vss_dig I P 0 volt power supply for the digital circuits. 12 vdd_dig I P 3.3 volt power supply for the digital circuits. 13 hsync IO D Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con- figured to be a master, (the default), this pin is an output and is the horizontal synchroni- zation pulse. When the sensor’s digital video port is configured to be a slave, this pin is an input and is the row trigger. 14 vsync IO D Digital Bidirectional. This is a dual mode pin. When the sensor’s digital video port is con- figured to be a master, (the default), this pin is an output and is the vertical synchroniza- tion pulse. When the sensor’s digital video port is configured to be a slave, this pin is an input and is the frame trigger. 15 pclk O D Digital output. The pixel clock. 16 mclk I D Digital input. The sensor’s master clock input. 17 d0 O D Digital output. Bit 0 of the digital video output bus. This output can be put into tri-state mode. 18 NC Pin not used, do not connect. 19 NC Pin not used, do not connect. 20 d1 O D Digital output. Bit 1 of the digital video output bus. This output can be put into tri-state mode. 21 d2 O D Digital output. Bit 2 of the digital video output bus. This output can be put into tri-state mode. 22 d3 O D Digital output. Bit 3 of the digital video output bus. This output can be put into tri-state mode. 23 d4 O D Digital output. Bit 4 of the digital video output bus. This output can be put into tri-state mode. 24 d5 O D Digital output. Bit 5 of the digital video output bus. This output can be put into tri-state mode. 25 d6 O D Digital output. Bit 6 of the digital video output bus. This output can be put into tri-state mode. |
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Mô tả tương tự - LM9617CCEA |
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