ADS5122 datasheet(11/19 Pages) TI

tên linh kiện	ADS5122

Giải thích chi tiết về linh kiện	8-Channel, 10-Bit, 65MSPS, 1.8V CMOS ANALOG-TO-DIGITAL CONVERTER

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ADS5122

11

SBAS272B

www.ti.com

APPLICATION INFORMATION

CONVERTER OPERATION

The ADS5122 is an 8-channel, simultaneous sampling ADC.

Its low power and high sampling rate of 65MSPS is achieved

using a state-of-the-art switched capacitor pipeline architec-

ture built on an advanced low-voltage CMOS process. The

ADS5122 primarily operates from a +1.8V single supply. For

additional interfacing flexibility, the digital I/O supply (DRVDD)

can be set to either +1.8V or +3.3V. The ADC core of each

channel consists of 10 pipeline stages. Each of the 10 stages

produces one digital bit per stage. Both the rising and the

falling clock edges are utilized to propagate the sample

through the pipeline every half clock, for a total of five clock

cycles. One and a half additional clock cycles are needed to

pass the sample data through the digital error correction logic

and the output latches. The total pipeline delay, or data

latency, is therefore 6.5 clock cycles long. Since a common

clock controls the timing of all eight channels, the analog

signal is sampled at the same time, as well as the data on the

parallel ports that become updated simultaneously.

INPUT IMPEDANCE

Due to the switched capacitor input, the input impedance of

the ADS5122 is effectively capacitive, and the driving source

needs to provide sufficient slew current to charge and dis-

charge the input sampling capacitor. The input impedance of

the ADS5122 is also a function of the sampling rate. As the

sampling frequency increases, the input impedance de-

creases at a linear rate of 1/fs. For most applications, this

does not represent a limitation since the impedance remains

relatively high, for example, approximately 20k

Ω at the max

sampling rate of 65MSPS. For applications using an op amp

to drive the ADC, it is recommended that a series resistor,

typically 10

Ω to 50Ω, be added between the amplifier output

and the converter inputs. This will isolate the converter’s

capacitive input from the driver and avoid potential gain

peaking, or instability.

INPUT BIASING

The ADS5122 operates from a single +1.8V analog supply,

and requires each of the analog inputs (AIN+, AIN–) to be

externally biased by a suitable common-mode voltage. For

example, with a common-mode voltage of +1V, the 1VPP full-

scale, differential input signal will swing symmetrically around

+1V, or between 0.75V and 1.25V. This is determined by the

two reference voltages, the top reference (REFT), and the

bottom reference (REFB). Typically, the input common-mode

level is related to the reference voltages and defined as

(REFT + REFB)/2. This reference mid-point is provided at the

common-mode level output (CML) pin and can directly be

used for input biasing purposes. The voltage at CML will

assume the mid-point for either internal or external reference

operation. In any case, it is recommended to bypass the CML

pin with a ceramic 0.1

µF capacitor.

DRIVING THE ANALOG INPUTS

Differential versus Single-Ended

The analog input of the ADS5122 allows it to be driven either

single-ended or differentially. Differential operation of the

ADS5122 requires an input signal that consists of an in-

phase and a 180

° out-of-phase part simultaneously applied

to the inputs (AIN+, AIN–). The full-scale input range of the

ADS5122 is defined by the reference voltages according to

FSR = 2 x (REFT – REFB). For a typical 1VPP range, the

differential input configuration only requires each input to see

a signal swing of 0.5VPP. Operating the converter in single-

ended configuration requires the full 1VPP swing applied to

the chosen input. The differential operation offers a number

of advantages, which in most applications will be instrumen-

tal in achieving the best dynamic performance of the ADS5122:

• Signal swing is half that required for the single-ended

operation and is therefore less demanding to achieve while

maintaining good linearity performance from the signal

source.

• Reduced signal swing allows for more headroom of the

interface circuitry and therefore a wider selection of the

best suitable driver op amp.

• Even-order harmonics are minimized.

• Improved noise immunity based on the converter’s com-

mon-mode input rejection.

For the single-ended mode, the signal is applied to one of the

inputs while the other input is biased with a DC voltage to the

required common-mode level. Both inputs are identical in

terms of their impedance and performance. Applying the

signal to the complementary input (AIN–) instead of the AIN+

input, however, will invert the orientation of the input signal

relative to the output code. This could be helpful, for ex-

ample, if the input driver operates in inverting mode using

input AIN– as the signal input will restore the phase of the

signal to its original orientation.

INPUT DRIVER CONFIGURATIONS

Transformer-Coupled Interface

If the application requires a signal conversion from a single-

ended source to drive the ADS5122 differentially, an RF-

transformer might be a good solution. The selected trans-

former must have a center tap in order to apply the common-

mode DC voltage necessary to bias the converter inputs. AC-

grounding the center tap will generate the differential signal

swing across the secondary winding. Consider a step-up

transformer to take advantage of signal amplification without

the introduction of another noise source. Furthermore, the

reduced signal swing from the source may lead to an im-

proved distortion performance.

Số phần tương tự - ADS5122

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Texas Instruments	ADS5122	504Kb / 21P	[Old version datasheet] 8-Channel, 10-Bit, 65MSPS, 1.8V CMOS ANALOG-TO-DIGITAL CONVERTER
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	ADS5122CZHK	504Kb / 21P	[Old version datasheet] 8-Channel, 10-Bit, 65MSPS, 1.8V CMOS ANALOG-TO-DIGITAL CONVERTER
	ADS5122	504Kb / 21P	[Old version datasheet] 8-Channel, 10-Bit, 65MSPS, 1.8V CMOS ANALOG-TO-DIGITAL CONVERTER

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