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ST16C2550CQ48 bảng dữ liệu(PDF) 8 Page - Exar Corporation |
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ST16C2550CQ48 bảng dữ liệu(HTML) 8 Page - Exar Corporation |
8 / 34 page ST16C2550 8 Rev. 3.20 GENERAL DESCRIPTION The 2550 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-to-paral- lel data conversions for both the transmitter and receiver sections. These functions are necessary for converting the serial data stream into parallel data that is required with digital data systems. Synchronization for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integ- rity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The 2550 represents such an integration with greatly enhanced features. The 2550 is fabricated with an advanced CMOS process. The 2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive FIFO memory, instead of none in the 16C2450. The 2550 is designed to work with high speed modems and shared network environments, that require fast data processing time. Increased performance is realized in the 2550 by the transmit and receive FIFOs. This allows the external processor to handle more network- ing tasks within a given time. For example, the ST16C2450 without a receive FIFO, will require un- loading of the RHR in 93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO less than every 100 microseconds. However with the 16 byte FIFO in the 2550, the data buffer will not require unloading/load- ing for 1.53 ms. This increases the service interval giving the external CPU additional time for other applications and reducing the overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is uniquely provided for maximum data throughput performance especially when operating in a multi-channel environment. The FIFO memory greatly reduces the bandwidth require- ment of the external controlling CPU, increases per- formance, and reduces power consumption. The 2550 is capable of operation to 1.5Mbps with a 24 MHz. With a crystal or external clock input of 7.3728 MHz the user can select data rates up to 460.8 Kbps. The rich feature set of the 2550 is available through internal registers. Selectable receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power on reset or an external reset, the 2550 is software compatible with the previous generation, ST16C2450. FUNCTIONAL DESCRIPTIONS UART A-B Functions The UART provides the user with the capability to Bi- directionally transfer information between an external CPU, the 2550 package, and an external serial de- vice. A logic 0 on chip select pins -CSA and/or -CSB allows the user to configure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 2 below. Table 2, SERIAL PORT SELECTION GUIDE CHIP SELECT Function -CS A-B = 1s None -CS A = 0 UART CHANNEL A -CS B = 0 UART CHANNEL B Internal Registers The 2550 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These resisters are shown in Table 3 below. The UART registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status and control registers (LCR/LSR), modem status and control registers (MCR/MSR), programmable data rate (clock) control registers (DLL/DLM), and a user assessable scratchpad register (SPR). |
Số phần tương tự - ST16C2550CQ48 |
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Mô tả tương tự - ST16C2550CQ48 |
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