công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
ST16C2550CJ44 bảng dữ liệu(PDF) 9 Page - Exar Corporation |
|
ST16C2550CJ44 bảng dữ liệu(HTML) 9 Page - Exar Corporation |
9 / 34 page ST16C2550 9 Rev. 3.20 Table 3, INTERNAL REGISTER DECODE A2 A1 A0 READ MODE WRITE MODE General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1* 0 0 0 Receive Holding Register Transmit Holding Register 0 0 1 Interrupt Enable Register 0 1 0 Interrupt Status Register FIFO Control Register 0 1 1 Line Control Register 1 0 0 Modem Control Register 1 0 1 Line Status Register 1 1 0 Modem Status Register 1 1 1 Scratchpad Register Scratchpad Register Baud Rate Register Set (DLL/DLM): Note *2 0 0 0 LSB of Divisor Latch LSB of Divisor Latch 0 0 1 MSB of Divisor Latch MSB of Divisor Latch Note 1* The General Register set is accessible only when CS A/B is a logic 0. Note 2* The Baud Rate register set is accessible only when CS A/B is a logic 0 and LCR bit-7 is a logic 1. FIFO Operation The 16 byte transmit and receive data FIFOs are enabled by the FIFO Control Register (FCR) bit-0. The user can set the receive trigger level via FCR bits 6- 7 but not the transmit trigger level. The transmit interrupt trigger level is set to 16 following a reset. The receiver FIFO section includes a time-out function to ensure data is delivered to the external CPU. An interrupt is generated whenever the Receive Holding Register (RHR) has not been read following the load- ing of a character or the receive trigger level has not been reached. Hardware/Software and Time-out Interrupts The interrupts are enabled by IER bits 0-3. Care must be taken when handling these interrupts. Following a reset the transmitter interrupt is enabled, the 2550 will issue an interrupt to indicate that transmit holding register is empty. This interrupt must be serviced prior to continuing operations. The LSR register provides the current singular highest priority interrupt only. It could be noted that CTS and RTS interrupts have lowest interrupt priority. A condition can exist where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the higher pending interrupt will the lower priority CTS/ RTS interrupt(s) be reflected in the status register. Servic- ing the interrupt without investigating further interrupt conditions can result in data errors. When two interrupt conditions have the same priority, it is important to service these interrupts correctly. Receive Data Ready and Receive Time Out have the same interrupt priority (when enabled by IER bit-3). The receiver issues an interrupt after the number of characters have reached the programmed trigger level. In this case the 2550 FIFO may hold more characters than the programmed trigger level. Follow- |
Số phần tương tự - ST16C2550CJ44 |
|
Mô tả tương tự - ST16C2550CJ44 |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |