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AD9144-M6720-EBZ bảng dữ liệu(PDF) 7 Page - Analog Devices

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AD9144
Data Sheet
Rev. A | Page 6 of 125
DIGITAL SPECIFICATIONS
AVDD33 = 3.3 V, SIOVDD33 = 3.3 V, IOVDD = 1.8 V, DVDD12 = 1.2 V, CVDD12 = 1.2 V, PVDD12 = 1.2 V, SVDD12 = 1.2 V, VTT = 1.2 V,
TA = −40°C to +85°C, IOUTFS = 20 mA, unless otherwise noted.
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
CMOS INPUT LOGIC LEVEL
Input Voltage (VIN) Logic
High
1.8 V
 IOVDD  3.3 V
0.7 × IOVDD
V
Low
1.8 V
 IOVDD  3.3 V
0.3 × IOVDD
V
CMOS OUTPUT LOGIC LEVEL
Output Voltage (VOUT) Logic
High
1.8 V
 IOVDD  3.3 V
0.75 × IOVDD
V
Low
1.8 V
 IOVDD  3.3 V
0.25 × IOVDD
V
MAXIMUM DAC UPDATE RATE1
1× interpolation2 (see Table 4)
1060
MSPS
2× interpolation3
2120
MSPS
4× interpolation
2800
MSPS
8× interpolation
2800
MSPS
ADJUSTED DAC UPDATE RATE
1× interpolation
1060
MSPS
2× interpolation
1060
MSPS
4× interpolation
700
MSPS
8× interpolation
350
MSPS
INTERFACE4
Number of JESD204B Lanes
8
Lanes
JESD204B Serial Interface Speed
Minimum
Per lane
1.44
Gbps
Maximum
Per lane, SVDD12 = 1.3 V ± 2%
10.6
Gbps
DAC CLOCK INPUT (CLK+, CLK−)
Differential Peak-to-Peak Voltage
400
1000
2000
mV
Common-Mode Voltage
Self biased input, ac-coupled
600
mV
Maximum Clock Rate
2800
MHz
REFCLK Frequency (PLL Mode)
6.0 GHz ≤ fVCO ≤ 12.0 GHz
35
1000
MHz
SYSTEM REFERENCE INPUT
(SYSREF+, SYSREF−)
Differential Peak-to-Peak
Voltage
400
1000
2000
mV
Common-Mode Voltage
0
2000
mV
SYSREF± Frequency5
fDATA/(K × S)
Hz
SYSREF TO DAC CLOCK6
SYSREF differential swing = 0.4 V, slew
rate = 1.3 V/ns, common modes tested:
ac-coupled, 0 V, 0.6 V, 1.25 V, 2.0 V
Setup Time
tSSD
131
ps
Hold Time
tHSD
119
ps
Keep Out Window
KOW
20
ps
SPI
Maximum Clock Rate
SCLK
IOVDD = 1.8 V
10
MHz
Minimum SCLK Pulse Width
High
tPWH
8
ns
Low
tPWL
12
ns
SDIO to SCLK
Setup Time
tDS
5
ns
Hold Time
tDH
2
ns


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