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AD9144BCPZRL bảng dữ liệu(PDF) 4 Page - Analog Devices |
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4 / 126 page  Data Sheet AD9144 Rev. A | Page 3 of 125 Step 4: Physical Layer..................................................................84 Step 5: Data Link Layer ..............................................................85 Step 6: Error Monitoring............................................................85 Register Maps and Descriptions....................................................86 Device Configuration Register Map.........................................86 Device Configuration Register Descriptions ..........................94 Outline Dimensions......................................................................124 Ordering Guide .........................................................................125 REVISION HISTORY 6/15—Rev. 0 to Rev. A Changed Functional Block Diagram Section to Typical Application Circuit Section..............................................................1 Changes to Figure 1...........................................................................1 Changed Detailed Functional Block Diagram Section to Functional Block Diagram Section.................................................4 Deleted Reference Voltage Parameter, Table 1 ..............................5 Changes to Output Voltage (VOUT) Logic High Parameter, Output Voltage (VOUT) Logic Low Parameter, and SYSREF± Frequency Parameter, Table 2..........................................................6 Changes to Table 4 ............................................................................7 Changes to Interpolation Parameter, Table 6 ................................8 Deleted Sync Off, Subclass Mode 0 Parameter, Table 7 ...............9 Changed Junction Temperature Parameter to Operating Junction Temperature, Table 10 ....................................................11 Changes to Terminology Section ..................................................15 Changes to Figure 26 Caption .......................................................19 Changes to Figure 29 Caption .......................................................20 Change to Device Revision Parameter, Table 14.........................24 Changes to Step 1: Start Up the DAC Section, Table 16, and Table 17.............................................................................................25 Changes to Step 3: Transport Layer Section and Table 19.........26 Changes to Table 20 and Table 21 .................................................27 Changes to Step 7: Optional Features Section.............................28 Added Table 25; Renumbered Sequentially.................................29 Changes to DAC PLL Setup Section and Table 26......................29 Changes to Lane0Checksum Section ...........................................30 Changes to Table 30 and Subclass 0 Section................................31 Changes to Table 33 ........................................................................32 Changes to Table 37 ........................................................................35 Changes to Table 38 ........................................................................36 Added SERDES PLL Fixed Register Writes Section and Table 39.............................................................................................36 Changes to Figure 38 and Table 40 ...............................................37 Changes to Figure 29 and Data Link Layer Section ...................38 Added Figure 42; Renumbered Sequentially ...............................39 Changes to Figure 44 ......................................................................40 Changes to Continuous Sync Mode (SYNCMOD = 0x2) Section ..............................................................................................42 Changes to Subclass 0 Section .......................................................43 Changes to Figure 53 ......................................................................50 Changes to Table 49 and Figure 54 ...............................................51 Changes to Table 50 and Figure 55 ...............................................52 Changes to Table 51 and Figure 56 ...............................................53 Changes to Table 52 and Figure 57 ...............................................54 Changes to Table 53, Table 54, and Figure 58 .............................55 Changes to Table 55 and Figure 59 ...............................................56 Changes to Table 56 and Figure 60 ...............................................57 Changes to Table 57 and Figure 61 ...............................................58 Changes to Table 58 and Figure 62 ...............................................59 Changes to Power Supply Recommendations Section...............63 Added Figure 64 ..............................................................................64 Changes to Figure 68 ......................................................................66 Changes to Table 66 ........................................................................67 Changes to Table 70, Table 71, Table 72, and I to Q Swap Section ..............................................................................................70 Changes to Power Detection and Protection Section ................72 Changes to DC Test Mode Section ...............................................73 Moved Figure 75 and Table 78 ......................................................75 Deleted Table 80; Renumbered Sequentially...............................76 Added DAC PLL Fixed Register Writes Section and Table 79.............................................................................................76 Changes to Clock Multiplication Section ....................................76 Added Loop Filter Section and Charge Pump Section ..............77 Added Temperature Tracking Section and Table 83 ..................78 Changes to Starting the PLL Section and Figure 79...................78 Changes to Transmit DAC Operation Section............................79 Changes to Self Calibration Section .............................................81 Added Figure 86 and Figure 87 .....................................................81 Changes to Device Power Dissipation Section............................82 Changes to Table 88 and Table 89.................................................83 Changes to Table 93 ........................................................................84 Changes to Table 94, Table 95, and Table 96 ...............................85 Changes to Table 97 ........................................................................86 Changes to Table 98 ........................................................................94 Deleted Lookup Tables for Three Different DAC PLL Reference Frequencies Section and Table 96 to Table 98...........................122 Added Figure 89 ............................................................................124 Updated Outline Dimensions......................................................124 Changes to Ordering Guide.........................................................125 7/14—Revision 0: Initial Version |
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